7
COMMERCIAL TEMPERATURE RANGE
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
WCLK
D
0
- D
7
WEN
RCLK
EF
Q
0
- Q
7
REN
t
DS
t
SKEW1
t
FRL
t
ENS
t
REF
t
A
D0
D1
(first valid write)
t
OLZ
(1)
t
ENS
D2
D3
OE
t
OE
t
A
D0
D1
2680 drw 07
NOTE:
1. tSKEW1 is the minimum time between a rising WCLK edge and a rising RCLK edge for EF to change during the current clock cycle. If the time between the rising edge of WCLK and the
rising edge of RCLK is less than tSKEW1, then EF may not change state until the next RCLK edge.
Figure 4. Read Cycle Timing
Figure 5. First Data Word Latency Timing
NOTE:
1. When tSKEW1 minimum specification, tFRL maximum = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timing apply only at the Empty Boundary (EF = LOW).
NO OPERATION
RCLK
REN
EF
t
CLK
t
CLKH
t
CLKL
t
ENS
t
ENH
t
REF
t
REF
VALID DATA
t
A
t
OLZ
t
OE
Q
0
- Q
7
OE
WCLK
(1)
t
SKEW1
WEN
t
OHZ
2680 drw 06
8
COMMERCIAL TEMPERATURE RANGE
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
Figure 6. Full Flag Timing
NOTE:
1. When tSKEW1 minimum specification, tFRL maximum = tCLK + tSKEW1
When tSKEW1 < minimum specification, tFRL maximum = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timing apply only at the Empty Boundary (EF = LOW).
Figure 7. Empty Flag Timing
WCLK
D
0
- D
7
WEN
RCLK
FF
t
SKEW1
t
WFF
DATA WRITE
REN
t
ENH
t
DS
t
SKEW1
t
ENS
NO WRITE NO WRITE
t
A
LOW
OE
t
ENS
t
WFF
t
ENS
Q
0
- Q
7
t
ENH
t
A
t
ENS
t
WFF
NEXT DATA READDATA READ
DATA IN OUTPUT REGISTER
2680 drw 08
NO WRITE
WCLK
D
0
- D
7
WEN
RCLK
EF
Q
0
- Q
7
OE
t
DS
t
ENS
t
REF
t
A
DATA WRITE 1
t
ENH
t
REF
t
DS
t
ENS
DATA WRITE 2
REN
DATA IN OUTPUT REGISTER
t
FRL
(1)
LOW
t
SKEW1
t
SKEW1
t
FRL
(1)
t
REF
DATA READ
2680 drw 09
t
ENH
9
COMMERCIAL TEMPERATURE RANGE
IDT72420/72200/72210/72220/72230/72240 CMOS SYNCFIFO™
64 x 8, 256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8, 4,096 x 8
NOTES:
1. tSKEW2 is the minimum time between a rising RCLK edge and a rising WCLK edge for AF to change during the current clock cycle. If the time between the rising edge of RCLK and the
rising edge of WCLK is less than tSKEW2, then AF may not change state until the next WCLK edge.
2. If a write is performed on this rising edge of the Write Clock, there will be Full -7 words in the FIFO when AF goes LOW.
Figure 8. Almost Full Flag Timing
NOTES:
1. tSKEW2 is the minimum time between a rising WCLK edge and a rising RCLK edge for AE to change during the current clock cycle. If the time between the rising edge of WCLK and the
rising edge of RCLK is less than tSKEW2, then AE may not change state until the next RCLK edge.
2. If a read is performed on this rising edge of the Read Clock, there will be Empty +7 words in the FIFO when AE goes LOW.
Figure 9. Almost Empty Flag Timing
WCLK
WEN
t
ENS
AE
t
ENH
t
CLKH
t
CLKL
t
AE
RCLK
REN
t
ENS
Empty+7
Empty+8
t
SKEW2
(1)
t
ENH
(2)
t
AE
2680 drw 11
WCLK
WEN
tENS
AF
tENH
tCLKH
tCLKL
RCLK
REN
tENS
tSKEW2
(1)
Full - 8 words in FIFO
Full - 7 words in FIFO
(2)
tAF
tAF
tENH
2680 drw10

72240L10TPG

Mfr. #:
Manufacturer:
IDT
Description:
FIFO 4K x 8 SyncFIFO 5.0V 10ns 8-bit port
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
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