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LTC4245IG#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36
LTC4245
4
4245fa
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
V
PB(TH)
Power Bad Threshold Voltage 12V
OUT
5V
OUT
, V
CFG
= 0V, Open
5V
OUT
When V
CFG
= V
CC
, 3V
OUT
V
EEOUT
, V
CFG
= 0V
●
●
●
●
10.8
4.5
2.8
–10.8
11.1
4.63
2.9
–11.1
11.4
4.75
3.0
–11.4
V
V
V
V
V
IN(TH)
Logic Input Threshold PGI, PCI_RST#, GPIOn
SDA, SCL
●
●
0.8
1.6
1.0
1.8
1.2
2.0
V
V
I
IN
Pin Input Current ON, PGI, PCI_RST#, V = 1.2V
SDA, SCL, ALERT#, GPIOn, HEALTHY#,
LOCAL_PCI_RST#, V = 6V
●
0±1 μA
V
OL
Output Low Voltage SDA, ALERT#, I = 5mA; GPIOn,
HEALTHY#, LOCAL_PCI_RST#, I = 3mA
●
0.2 0.4 V
V
TRI(H)
ADR2, ADR3, CFG Input High Threshold
●
V
CC
–0.8 V
CC
–0.4 V
CC
–0.2 V
V
TRI(L)
ADRn, CFG Input Low Threshold
●
0.2 0.4 0.8 V
I
TRI(IN,HL)
ADR2, ADR3, CFG High, Low Input
Current
V = 0V, V
CC
●
±80 μA
I
TRI(IN,Z)
ADR2, ADR3, CFG High Z Input Current V = 0.8V, V
CC
–0.8V
●
±10 μA
I
ADR01(IN)
ADR0, ADR1 Input Current V
ADR0
, V
ADR1
= 0V, V
CC
●
–30 1 μA
I
SENSE
Sense Pin Input Current
12V
SENSE
, 5V
SENSE
, 3V
SENSE
V
EESENSE
After Start-Up
V
SENSE
= V
IN
V
VEESENSE
= –12V
●
●
0.3
–30
1
–45
μA
μA
I
OUT(ON)
OUT Pin Input Current V
12VOUT
= 12V, V
ON
= 2V
V
5VOUT
= 5V, V
ON
= 2V
V
3VOUT
= 3.3V, V
ON
= 2V
V
VEEOUT
= –12V, V
ON
= 2V
●
●
●
●
200
275
75
–200
280
390
105
–280
μA
μA
μA
μA
R
OUT(DIS)
OUT Pin Discharge Resistance V
12VOUT
= 6V, V
ON
= 0V
V
5VOUT
= 3V, V
ON
= 0V
V
3VOUT
= 2V, V
ON
= 0V
V
VEEOUT
= –6V, V
ON
= 0V
●
●
●
●
650
125
130
1300
1000
180
190
1800
1800
325
340
3200
Ω
Ω
Ω
Ω
I
VEEOUT(UP)
V
EEOUT
Pull-Up Current V
VEEOUT
= 0V
●
–36 –54 μA
V
PXG
PRECHARGE Voltage I
PRECHARGE
= Open, –70mA (Note 6)
●
0.95 1 1.05 V
Timer, Soft-Start
V
TIMER(H)
TIMER Pin High Threshold V
TIMER
Rising
●
2.5 2.56 2.62 V
V
TIMER(L)
TIMER Pin Low Threshold V
TIMER
Falling
●
0.1 0.23 0.4 V
I
TIMER
TIMER Pin Pull-Up Current During Start-Up, V
TIMER
= 0V
During PGI Timeout, V
TIMER
= 0V
During Auto-Retry, V
TIMER
= 0V
●
●
●
–80
–8
–1.5
–100
–10
–2
–120
–12
–2.5
μA
μA
μA
K
TMRATIO
TIMER Pin Current Ratio (I
TIMER(RTRY)
/I
TIMER(START)
)
●
1.6 2 2.7 %
K
TMCAP
Start-Up Time per TIMER Capacitance ((V
TIMER(H)
– V
TIMER(L)
)/I
TIMER(START)
)
●
20 23.3 26 ms/μF
I
SS
SS Pin Pull-Up Current Fast Ramp, V
SS
= 0V
Slow Ramp, V
SS
= 2V
●
●
–16
–1.5
–20
–2
–24
–2.5
μA
μA
R
TS(DIS)
TIMER, SS Discharge Resistance V
TIMER
= 1.2V, V
SS
= 1.2V
●
225 400
Ω
G
SS
Gain from SS Pin to Foldback Current
Limit (ΔV
SNS(FB)
/ΔV
SS
)
12V
IN
, V
EEIN
5V
IN
, 3V
IN
46
23
mV/V
mV/V
The ● denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at T
A
= 25°C. V
12VIN
= 12V, V
5VIN
= 5V, V
3VIN
= 3.3V, V
VEEIN
= –12V, unless otherwise noted.
ELECTRICAL CHARACTERISTICS
LTC4245
5
4245fa
The ● denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at T
A
= 25°C. V
12VIN
= 12V, V
5VIN
= 5V, V
3VIN
= 3.3V, V
VEEIN
= –12V, unless otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ADC
RES Resolution (No Missing Codes) (Note 7)
●
8 Bits
V
FS
Full-Scale Voltage (V
FS
= 255LSB)
12V
IN
, 12V
OUT
12V
IN
– 12V
SENSE
,
V
EESENSE
– V
EEIN
5V
IN
, 5V
OUT
5V
IN
– 5V
SENSE
, 3V
IN
– 3V
SENSE
3V
IN
, 3V
OUT
V
EEIN
, V
EEOUT
GPIO
(Note 6)
V
CFG
= 0V, Open
V
CFG
= V
CC
●
●
●
●
●
●
●
●
13.744
62.47
5.5
3.75
31.24
3.75
–13.744
2.5
14.025
63.75
5.61
3.825
31.875
3.825
–14.025
2.55
14.306
65.03
5.72
3.9
32.51
3.9
–14.306
2.6
V
mV
V
V
mV
V
V
V
INL Integral Nonlinearity ΔV
SENSE
(Note 8)
Other 9 Channels
●
●
±0.5
±0.2
±2
±1.25
LSB
LSB
OE Offset Error ΔV
SENSE
(Note 6)
V
EEIN
, V
EEOUT
Other 7 Channels
●
●
●
±0.5
±0.5
±0.3
±1.5
±1.25
±1
LSB
LSB
LSB
FSE Full-Scale Error
●
±5 LSB
TUE Total Unadjusted Error
●
±5 LSB
t
ADC
Conversion Time All 13 Channels Once
ΔV
SENSE
, V
EEIN
, V
EEOUT
Other 7 Channels
665
70
35
ms
ms
ms
Delays
t
D
Turn-On Delay
●
60 100 150 ms
t
PLH(GATE)
Input High (ON) to Gates High Delay SS Open
●
15 30 μs
t
PHL(GATE)
Input High (BD_SEL#), Input Low (ON)
to Gates Low Propagation Delay
C
GATE
= 1pF
●
0.3 1 μs
t
PHL(UVL)
Supply Low to Gates Low Delay 12V
IN
, 5V
IN
, 3V
IN
, C
GATE
= 1pF
V
EEIN
, C
VEEGATE
= 1pF
●
●
2.1
3.3
3.5
5.5
4.9
7.7
μs
μs
t
CB
Circuit Breaker Filter Delay Time
●
16 22 28 μs
t
ACL
Active Current Limit Delay ΔV
12VSENSE
= 300mV, C
12VGATE
= 10nF
ΔV
5VSENSE
= 150mV, C
5VGATE
= 10nF
ΔV
3VSENSE
= 150mV, C
3VGATE
= 10nF
ΔV
VEESENSE
= 300mV, C
VEEGATE
= 10nF
●
●
●
●
0.9
0.85
0.7
2
2.3
2.1
1.8
5
μs
μs
μs
μs
t
PHL(PGI)
PGI Low to Gates Low C
GATE
= 1pF
●
12 20 28 μs
t
PHL(RST)
Output Low to LOCAL_PCI_RST# Low 12V
OUT
, 5V
OUT
, 3V
OUT
, V
PCI_RST#
= 2V
V
EEOUT
, V
PCI_RST#
= 2V
●
●
9
10.2
15
17
21
23.8
μs
μs
t
P(RST)
PCI_RST# to LOCAL_PCI_RST# Delay
●
60 200 ns
I
2
C Interface Timing (Note 7)
f
SCL(MAX)
Maximum SCL Clock Frequency Operates with f
SCL
≤ f
SCL(MAX)
400 kHz
t
BUF(MIN)
Min. Bus Free Time Between Stop/Start 0.12 1.3 μs
t
SU, STA(MIN)
Minimum Repeated Start Set-Up Time 10 600 ns
t
HD, STA(MIN)
Min. Hold Time After (Repeated) Start 140 600 ns
t
SU, STO(MIN)
Minimum Stop Condition Set-Up Time 10 600 ns
ELECTRICAL CHARACTERISTICS
LTC4245
6
4245fa
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
t
SU, DAT(MIN)
Minimum Data Set-Up Time Input 0 100 ns
t
HD, DATI(MIN)
Minimum Data Hold Time Input –100 0 ns
t
HD, DATO(MIN)
Minimum Data Hold Time Output 300 500 900 ns
t
SP(MAX)
Maximum Suppressed Spike Pulse Width 50 110 250 ns
C
X
SCL, SDA Input Capacitance 5 10 pF
t
of
Data Output Fall Time (Note 9) 20 + 0.1C
b
250 ns
The ● denotes the specifi cations which apply over the full operating temperature
range, otherwise specifi cations are at T
A
= 25°C. V
12VIN
= 12V, V
5VIN
= 5V, V
3VIN
= 3.3V, V
VEEIN
= –12V, unless otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to GND unless otherwise
specifi ed.
Note 3: The 5V
GATE
and 3V
GATE
pins should not be driven beyond the
lower of 12V
IN
+ 0.3V and 14V.
Note 4: An internal clamp limits the GATE pins to a minimum of 5V above
V
OUT
(V
EEIN
for V
EEGATE
). Driving this pin to voltages beyond the clamp
may damage the device.
Note 5: The device pulls up the V
EEOUT
pin to 0.6V when pin is in open state.
Note 6: UHF package specifi cation limits are identical to G package limits
and guaranteed by design and by correlation to wafer test measurements.
Note 7: Guaranteed by design and not subject to test.
Note 8: Integral Nonlinearity is defi ned as the deviation of a code from a
precise analog input voltage. Maximum specifi cations are limited by the
LSB step size and the single shot measurement. Typical specifi cations are
measured from 1/4, 1/2, 3/4 areas of the quantization band.
Note 9: C
b
= total capacitance of one bus line in pF.
TI I G DIAGRA
WUW
t
SU, DAT
t
SU, STO
t
SU, STA
t
BUF
t
HD, STA
t
SP
t
SP
t
HD, DATO,
t
HD, DATI
t
HD, STA
t
of
START
CONDITION
STOP
CONDITION
REPEATED START
CONDITION
START
CONDITION
SDA
SCL
4245 TDO1
ELECTRICAL CHARACTERISTICS
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36

LTC4245IG#PBF

Mfr. #:
Buy LTC4245IG#PBF
Manufacturer:
Analog Devices Inc.
Description:
Hot Swap Voltage Controllers Quad Hot Swap Contr. w/ADC and I2C
Lifecycle:
New from this manufacturer.
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