Data Sheet AD1974
Rev. D | Page 11 of 24
THEORY OF OPERATION
ANALOG-TO-DIGITAL CONVERTERS (ADCS)
There are four ADC channels in the AD1974 configured as two
stereo pairs with differential inputs. The ADCs can operate at a
nominal sample rate of 48 kHz, 96 kHz, or 192 kHz. The ADCs
include on-board digital antialiasing filters with a 79 dB stop-
band attenuation and a linear phase response, operating at
an oversampling ratio of 128 (48 kHz, 96 kHz, and 192 kHz
modes). Digital outputs are supplied through two serial data
output pins (one for each stereo pair) as well as a common
frame (ALRCLK) and bit clock (ABCLK). Alternatively, one
of the time division multiplexed (TDM) modes can be used
to access up to 16 channels on a single TDM data line.
The ADCs must be driven from a differential signal source for
best performance. The input pins of the ADCs connect to inter-
nal switched capacitors. To isolate the external driving op amp
from the glitches caused by the internal switched capacitors,
each input pin should be isolated by using a series connected,
external, 100 Ω resistor together with a 1 nF capacitor connected
from each input to ground. This capacitor must be of high quality,
for instance, a ceramic NP0 capacitor or a polypropylene film
The differential inputs have a nominal common-mode voltage
of 1.5 V. The voltage at the common-mode reference pin (CM)
can be used to bias external op amps to buffer the input signals
(see the Power Supply and Voltage Reference section). The inputs
can also be ac-coupled and do not need an external dc bias to CM.
A digital high-pass filter can be switched in line with the ADCs
under serial control to remove residual dc offsets. It has a 1.4 Hz,
6 dB per octave cutoff at a 48 kHz sample rate. The cutoff fre-
quency scales directly with sample frequency.
The voltage at CM can be used to bias the external op amps that
buffer the output signals (see the Power Supply and Voltage
The on-chip PLL can be selected to reference the input sample
rate from either the LRCLK or AUXLRCK pins or 256, 384, 512,
or 768 times the sample rate, referenced to the 48 kHz mode from
the MCLKI/XI pin. The default at power-up is 256 × f
MCLKI. In 96 kHz mode, the master clock frequency stays
at the same absolute frequency; therefore, the actual mul-
tiplication rate is divided by 2. In 192 kHz mode, the actual
multiplication rate is divided by 4. For example, if the AD1974
is programmed in 256 × f
mode, the frequency of the master
clock input is 256 × 48 kHz = 12.288 MHz. If the AD1974 is
then switched to 96 kHz operation (by writing to the SPI
port), the frequency of the master clock should remain at
12.288 MHz (128 × f
). In 192 kHz mode, this becomes 64 × f
The internal clock for the ADCs is 256 × f
for all clock modes.
By default, the on-board PLL generates this internal master clock
from an external clock. A direct 512 × f
(referenced to 48 kHz
mode) master clock can be used for the ADCs if selected in the
PLL and Clock Control 1 register.
Note that it is not possible to use a direct clock for the ADCs
set to the 192 kHz mode. It is required that the on-chip PLL be
used in this mode.
The PLL can be powered down in the PLL and Clock Control 0
register. To ensure reliable locking when changing PLL modes,
or if the reference clock is unstable at power-on, power down
the PLL and then power it back up when the reference clock has
The internal MCLK can be disabled in the PLL and Clock Control
0 register to reduce power dissipation when the AD1974 is idle.
The clock should be stable before it is enabled. Unless a stand-
alone mode is selected (see the Serial Control Port section), the
clock is disabled by reset and must be enabled by writing to the
SPI port for normal operation.
To maintain the highest performance possible, it is recom-
mended that the clock jitter of the internal master clock signal
be limited to less than 300 ps rms time interval error (TIE). Even
at these levels, extra noise or tones can appear in the outputs if
the jitter spectrum contains large spectral peaks. If the internal
PLL is not being used, it is highly recommended that an inde-
pendent crystal oscillator generate the master clock. In addition,
it is especially important that the clock signal should not be
passed through an FPGA, CPLD, DSP, or other large digital
chip before being applied to the AD1974. In most cases, this
induces clock jitter due to the sharing of common power and
ground connections with other unrelated digital output signals.
When the PLL is used, jitter in the reference clock is attenuated
above a certain frequency depending on the loop filter.
RESET AND POWER-DOWN
The reset pin sets all the control registers to their default settings.
To avoid pops, reset does not power down the analog outputs.
After reset is deasserted, and the PLL acquires a lock condition,
an initialization routine runs inside the AD1974. This initializa-
tion lasts for approximately 256 master clock cycles.
The PLL and Clock Control 0 register and the ADC Control 1
register power down their respective sections using power down
bits. All other register settings are retained. The
should be pulled low by an external resistor to guarantee proper