Embedded Memory Configurations for Single-port Mode
Table 19. Single-port Embedded Memory Configurations for Intel Arria 10 Devices
This table lists the maximum configurations supported for single-port RAM and ROM modes.
Memory Block Depth (bits) Programmable Width
MLAB 32 x16, x18, or x20
64
(10)
x8, x9, x10
M20K 512 x40, x32
1K x20, x16
2K x10, x8
4K x5, x4
8K x2
16K x1
Clock Networks and PLL Clock Sources
The clock network architecture is based on Intel's global, regional, and peripheral
clock structure. This clock structure is supported by dedicated clock input pins,
fractional clock synthesis PLLs, and integer I/O PLLs.
Clock Networks
The Intel Arria 10 core clock networks are capable of up to 800 MHz fabric operation
across the full industrial temperature range. For the external memory interface, the
clock network supports the hard memory controller with speeds up to 2,400 Mbps in a
quarter-rate transfer.
To reduce power consumption, the Intel Quartus Prime software identifies all unused
sections of the clock network and powers them down.
Fractional Synthesis and I/O PLLs
Intel Arria 10 devices contain up to 32 fractional synthesis PLLs and up to 16 I/O PLLs
that are available for both specific and general purpose uses in the core:
Fractional synthesis PLLs—located in the column adjacent to the transceiver blocks
I/O PLLs—located in each bank of the 48 I/Os
Fractional Synthesis PLLs
You can use the fractional synthesis PLLs to:
Reduce the number of oscillators that are required on your board
Reduce the number of clock pins that are used in the device by synthesizing
multiple clock frequencies from a single reference clock source
(10)
Supported through software emulation and consumes additional MLAB blocks.
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The fractional synthesis PLLs support the following features:
Reference clock frequency synthesis for transceiver CMU and Advanced Transmit
(ATX) PLLs
Clock network delay compensation
Zero-delay buffering
Direct transmit clocking for transceivers
Independently configurable into two modes:
Conventional integer mode equivalent to the general purpose PLL
Enhanced fractional mode with third order delta-sigma modulation
PLL cascading
I/O PLLs
The integer mode I/O PLLs are located in each bank of 48 I/Os. You can use the I/O
PLLs to simplify the design of external memory and high-speed LVDS interfaces.
In each I/O bank, the I/O PLLs are adjacent to the hard memory controllers and LVDS
SERDES. Because these PLLs are tightly coupled with the I/Os that need to use them,
it makes it easier to close timing.
You can use the I/O PLLs for general purpose applications in the core such as clock
network delay compensation and zero-delay buffering.
Intel Arria 10 devices support PLL-to-PLL cascading.
FPGA General Purpose I/O
Intel Arria 10 devices offer highly configurable GPIOs. Each I/O bank contains 48
general purpose I/Os and a high-efficiency hard memory controller.
The following list describes the features of the GPIOs:
Consist of 3 V I/Os for high-voltage application and LVDS I/Os for differential
signaling
Up to two 3 V I/O banks, available in some devices, that support up to 3 V I/O
standards
LVDS I/O banks that support up to 1.8 V I/O standards
Support a wide range of single-ended and differential I/O interfaces
LVDS speeds up to 1.6 Gbps
Each LVDS pair of pins has differential input and output buffers, allowing you to
configure the LVDS direction for each pair.
Programmable bus hold and weak pull-up
Programmable differential output voltage (V
OD
) and programmable pre-emphasis
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Series (R
S
) and parallel (R
T
) on-chip termination (OCT) for all I/O banks with OCT
calibration to limit the termination impedance variation
On-chip dynamic termination that has the ability to swap between series and
parallel termination, depending on whether there is read or write on a common
bus for signal integrity
Easy timing closure support using the hard read FIFO in the input register path,
and delay-locked loop (DLL) delay chain with fine and coarse architecture
External Memory Interface
Intel Arria 10 devices offer massive external memory bandwidth, with up to seven 32-
bit DDR4 memory interfaces running at up to 2,400 Mbps. This bandwidth provides
additional ease of design, lower power, and resource efficiencies of hardened high-
performance memory controllers.
The memory interface within Intel Arria 10 FPGAs and SoCs delivers the highest
performance and ease of use. You can configure up to a maximum width of 144 bits
when using the hard or soft memory controllers. If required, you can bypass the hard
memory controller and use a soft controller implemented in the user logic.
Each I/O contains a hardened DDR read/write path (PHY) capable of performing key
memory interface functionality such as read/write leveling, FIFO buffering to lower
latency and improve margin, timing calibration, and on-chip termination.
The timing calibration is aided by the inclusion of hard microcontrollers based on
Intel's Nios
®
II technology, specifically tailored to control the calibration of multiple
memory interfaces. This calibration allows the Intel Arria 10 device to compensate for
any changes in process, voltage, or temperature either within the Intel Arria 10 device
itself, or within the external memory device. The advanced calibration algorithms
ensure maximum bandwidth and robust timing margin across all operating conditions.
In addition to parallel memory interfaces, Intel Arria 10 devices support serial memory
technologies such as the Hybrid Memory Cube (HMC). The HMC is supported by the
Intel Arria 10 high-speed serial transceivers which connect up to four HMC links, with
each link running at data rates up to 15 Gbps.
Related Information
External Memory Interface Spec Estimator
Provides a parametric tool that allows you to find and compare the performance of
the supported external memory interfaces in IntelFPGAs.
Memory Standards Supported by Intel Arria 10 Devices
The I/Os are designed to provide high performance support for existing and emerging
external memory standards.
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10AS048H4F34I3SG

Mfr. #:
Manufacturer:
Intel / Altera
Description:
FPGA - Field Programmable Gate Array Arria 10 SX 480 SoC FPGA
Lifecycle:
New from this manufacturer.
Delivery:
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