PCS Description
Standard PCS Operates at a data rate up to 12 Gbps
Supports protocols such as PCI-Express, CPRI 4.2+, GigE, IEEE 1588 in Hard PCS
Implements other protocols using Basic/Custom (Standard PCS) transceiver
configuration rules.
Enhanced PCS Performs functions common to most serial data industry standards, such as word
alignment, encoding/decoding, and framing, before data is sent or received off-chip
through the PMA
Handles data transfer to and from the FPGA fabric
Handles data transfer internally to and from the PMA
Provides frequency compensation
Performs channel bonding for multi-channel low skew applications
PCIe Gen3 PCS Supports the seamless switching of Data and Clock between the Gen1, Gen2, and Gen3
data rates
Provides support for PIPE 3.0 features
Supports the PIPE interface with the Hard IP enabled, as well as with the Hard IP
bypassed
Related Information
PCIe Gen1, Gen2, and Gen3 Hard IP on page 26
Interlaken Support on page 26
10 Gbps Ethernet Support on page 26
PCS Protocol Support
This table lists some of the protocols supported by the Intel Arria 10 transceiver PCS.
For more information about the blocks in the transmitter and receiver data paths,
refer to the related information.
Protocol
Data Rate
(Gbps)
Transceiver IP PCS Support
PCIe Gen3 x1, x2, x4, x8 8.0 Native PHY (PIPE) Standard PCS and PCIe
Gen3 PCS
PCIe Gen2 x1, x2, x4, x8 5.0 Native PHY (PIPE) Standard PCS
PCIe Gen1 x1, x2, x4, x8 2.5 Native PHY (PIPE) Standard PCS
1000BASE-X Gigabit Ethernet 1.25 Native PHY Standard PCS
1000BASE-X Gigabit Ethernet with
IEEE 1588v2
1.25 Native PHY Standard PCS
10GBASE-R 10.3125 Native PHY Enhanced PCS
10GBASE-R with IEEE 1588v2 10.3125 Native PHY Enhanced PCS
10GBASE-R with KR FEC 10.3125 Native PHY Enhanced PCS
10GBASE-KR and 1000BASE-X 10.3125 1G/10GbE and 10GBASE-KR PHY Standard PCS and
Enhanced PCS
Interlaken (CEI-6G/11G) 3.125 to 17.4 Native PHY Enhanced PCS
SFI-S/SFI-5.2 11.2 Native PHY Enhanced PCS
10G SDI 10.692 Native PHY Enhanced PCS
continued...
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Protocol Data Rate
(Gbps)
Transceiver IP PCS Support
CPRI 6.0 (64B/66B) 0.6144 to
10.1376
Native PHY Enhanced PCS
CPRI 4.2 (8B/10B) 0.6144 to
9.8304
Native PHY Standard PCS
OBSAI RP3 v4.2 0.6144 to 6.144 Native PHY Standard PCS
SD-SDI/HD-SDI/3G-SDI 0.143
(12)
to
2.97
Native PHY Standard PCS
Related Information
Intel Arria 10 Transceiver PHY User Guide
Provides more information about the supported transceiver protocols and PHY IP,
the PMA architecture, and the standard, enhanced, and PCIe Gen3 PCS
architecture.
SoC with Hard Processor System
Each SoC device combines an FPGA fabric and a hard processor system (HPS) in a
single device. This combination delivers the flexibility of programmable logic with the
power and cost savings of hard IP in these ways:
Reduces board space, system power, and bill of materials cost by eliminating a
discrete embedded processor
Allows you to differentiate the end product in both hardware and software, and to
support virtually any interface standard
Extends the product life and revenue through in-field hardware and software
updates
(12)
The 0.143 Gbps data rate is supported using oversampling of user logic that you must
implement in the FPGA fabric.
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Figure 9. HPS Block Diagram
This figure shows a block diagram of the HPS with the dual ARM Cortex-A9 MPCore processor.
ARM Cortex-A9
QSPI Flash
Control
UART
(x2)
ARM Cortex-A9
512 KB L2 Cache
EMAC (x3)
JTAG Debug/
Trace
USB OTG
(x2)
I
2
C
(x5)
Hard Processor System (HPS)
256 KB
RAM
Timers
(x11)
LW HPS to
Core Bridge
HPS to Core
Bridge
Core to HPS
Bridge
MPFE
32 KB L1 Cache 32 KB L1 Cache
NEON FPU NEON FPU
AXI 32 AXI 32/64/128 AXI 32/64/128
A
C
P
SPI
(x2)
NAND Flash
with ECC
With integrated DMA
To hard memory
controller
SD/SDIO/
MMC
DMA
(8 Channels)
Dedicated
HPS I/O
FPGA
Configuration
Key Advantages of 20-nm HPS
The 20-nm HPS strikes a balance between enabling maximum software compatibility
with 28-nm SoCs while still improving upon the 28-nm HPS architecture. These
improvements address the requirements of the next generation target markets such
as wireless and wireline communications, compute and storage equipment, broadcast
and military in terms of performance, memory bandwidth, connectivity via backplane
and security.
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10AS048H4F34I3SG

Mfr. #:
Manufacturer:
Intel / Altera
Description:
FPGA - Field Programmable Gate Array Arria 10 SX 480 SoC FPGA
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union