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10AS048H4F34I3SG

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FPGA Configuration and HPS Booting
The FPGA fabric and HPS in the SoC FPGA must be powered at the same time. You can
reduce the clock frequencies or gate the clocks to reduce dynamic power.
Once powered, the FPGA fabric and HPS can be configured independently thus
providing you with more design flexibility:
• You can boot the HPS independently. After the HPS is running, the HPS can fully or
partially reconfigure the FPGA fabric at any time under software control. The HPS
can also configure other FPGAs on the board through the FPGA configuration
controller.
• Configure the FPGA fabric first, and then boot the HPS from memory accessible to
the FPGA fabric.
Hardware and Software Development
For hardware development, you can configure the HPS and connect your soft logic in
the FPGA fabric to the HPS interfaces using the Platform Designer system integration
tool in the Intel Quartus Prime software.
For software development, the ARM-based SoC FPGA devices inherit the rich software
development ecosystem available for the ARM Cortex-A9 MPCore processor. The
software development process for Intel SoC FPGAs follows the same steps as those for
other SoC devices from other manufacturers. Support for Linux*, VxWorks*, and other
operating systems are available for the SoC FPGAs. For more information on the
operating systems support availability, contact the Intel FPGA sales team.
You can begin device-specific firmware and software development on the Intel SoC
FPGA Virtual Target. The Virtual Target is a fast PC-based functional simulation of a
target development system—a model of a complete development board. The Virtual
Target enables the development of device-specific production software that can run
unmodified on actual hardware.
Dynamic and Partial Reconfiguration
The Intel Arria 10 devices support dynamic and partial reconfiguration. You can use
dynamic and partial reconfiguration simultaneously to enable seamless reconfiguration
of both the device core and transceivers.
Dynamic Reconfiguration
You can reconfigure the PMA and PCS blocks while the device continues to operate.
This feature allows you to change the data rates, protocol, and analog settings of a
channel in a transceiver bank without affecting on-going data transfer in other
transceiver banks. This feature is ideal for applications that require dynamic
multiprotocol or multirate support.
Partial Reconfiguration
Using partial reconfiguration, you can reconfigure some parts of the device while
keeping the device in operation.
Intel
®
Arria
®
10 Device Overview
A10-OVERVIEW | 2018.04.09
Intel
®
Arria
®
10 Device Overview
37
Instead of placing all device functions in the FPGA fabric, you can store some functions
that do not run simultaneously in external memory and load them only when required.
This capability increases the effective logic density of the device, and lowers cost and
power consumption.
In the Intel solution, you do not have to worry about intricate device architecture to
perform a partial reconfiguration. The partial reconfiguration capability is built into the
Intel Quartus Prime design software, making such time-intensive task simple.
Intel Arria 10 devices support partial reconfiguration in the following configuration
options:
• Using an internal host:
— All supported configuration modes where the FPGA has access to external
memory devices such as serial and parallel flash memory.
— Configuration via Protocol [CvP (PCIe)]
• Using an external host—passive serial (PS), fast passive parallel (FPP) x8,
FPP x16, and FPP x32 I/O interface.
Enhanced Configuration and Configuration via Protocol
Table 25. Configuration Schemes and Features of Intel Arria 10 Devices
Intel Arria 10 devices support 1.8 V programming voltage and several configuration schemes.
Scheme Data
Width
Max Clock
Rate
(MHz)
Max Data
Rate
(Mbps)
(13)
Decompression Design
Security
(1
4)
Partial
Reconfiguration
(15)
Remote
System
Update
JTAG 1 bit 33 33 — — Yes
(16)
—
Active Serial (AS)
through the
EPCQ-L
configuration
device
1 bit,
4 bits
100 400 Yes Yes Yes
(16)
Yes
Passive serial (PS)
through CPLD or
external
microcontroller
1 bit 100 100 Yes Yes Yes
(16)
Parallel
Flash
Loader
(PFL) IP
core
continued...
(13)
Enabling either compression or design security features affects the maximum data rate. Refer
to the Intel Arria 10 Device Datasheet for more information.
(14)
Encryption and compression cannot be used simultaneously.
(15)
Partial reconfiguration is an advanced feature of the device family. If you are interested in
using partial reconfiguration, contact Intel for support.
(16)
Partial configuration can be performed only when it is configured as internal host.
Intel
®
Arria
®
10 Device Overview
A10-OVERVIEW | 2018.04.09
Intel
®
Arria
®
10 Device Overview
38
Scheme Data
Width
Max Clock
Rate
(MHz)
Max Data
Rate
(Mbps)
(13)
Decompression Design
Security
(1
4)
Partial
Reconfiguration
(15)
Remote
System
Update
Fast passive
parallel (FPP)
through CPLD or
external
microcontroller
8 bits 100 3200 Yes Yes Yes
(17)
PFL IP
core
16 bits Yes Yes
32 bits Yes Yes
Configuration via
HPS
16 bits 100 3200 Yes Yes Yes
(17)
—
32 bits Yes Yes
Configuration via
Protocol [CvP
(PCIe*)]
x1, x2,
x4, x8
lanes
— 8000 Yes Yes Yes
(16)
—
You can configure Intel Arria 10 devices through PCIe using Configuration via Protocol
(CvP). The Intel Arria 10 CvP implementation conforms to the PCIe 100 ms
power-up-to-active time requirement.
SEU Error Detection and Correction
Intel Arria 10 devices offer robust and easy-to-use single-event upset (SEU) error
detection and correction circuitry.
The detection and correction circuitry includes protection for Configuration RAM
(CRAM) programming bits and user memories. The CRAM is protected by a
continuously running CRC error detection circuit with integrated ECC that
automatically corrects one or two errors and detects higher order multi-bit errors.
When more than two errors occur, correction is available through reloading of the core
programming file, providing a complete design refresh while the FPGA continues to
operate.
The physical layout of the Intel Arria 10 CRAM array is optimized to make the majority
of multi-bit upsets appear as independent single-bit or double-bit errors which are
automatically corrected by the integrated CRAM ECC circuitry. In addition to the CRAM
protection, the M20K memory blocks also include integrated ECC circuitry and are
layout-optimized for error detection and correction. The MLAB does not have ECC.
Power Management
Intel Arria 10 devices leverage the advanced 20 nm process technology, a low 0.9 V
core power supply, an enhanced core architecture, and several optional power
reduction techniques to reduce total power consumption by as much as 40%
compared to Arria V devices and as much as 60% compared to Stratix V devices.
(13)
Enabling either compression or design security features affects the maximum data rate. Refer
to the Intel Arria 10 Device Datasheet for more information.
(14)
Encryption and compression cannot be used simultaneously.
(15)
Partial reconfiguration is an advanced feature of the device family. If you are interested in
using partial reconfiguration, contact Intel for support.
(17)
Supported at a maximum clock rate of 100 MHz.
Intel
®
Arria
®
10 Device Overview
A10-OVERVIEW | 2018.04.09
Intel
®
Arria
®
10 Device Overview
39
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10AS048H4F34I3SG

Mfr. #:
Buy 10AS048H4F34I3SG
Manufacturer:
Intel / Altera
Description:
FPGA - Field Programmable Gate Array Arria 10 SX 480 SoC FPGA
Lifecycle:
New from this manufacturer.
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