Product Line U19
(19 mm × 19 mm,
484-pin UBGA)
F27
(27 mm × 27 mm,
672-pin FBGA)
F29
(29 mm × 29 mm,
780-pin FBGA)
F34
(35 mm × 35 mm,
1152-pin FBGA)
3 V
I/O
LVDS
I/O
XCVR 3 V
I/O
LVDS
I/O
XCVR 3 V
I/O
LVDS
I/O
XCVR 3 V
I/O
LVDS
I/O
XCVR
SX 480 48 312 12 48 444 24
SX 570 48 444 24
SX 660 48 444 24
Table 14. Package Plan for Intel Arria 10 SX Devices (F35, KF40, and NF40)
Refer to I/O and High Speed I/O in Intel Arria 10 Devices chapter for the number of 3 V I/O, LVDS I/O, and
LVDS channels in each device package.
Product Line F35
(35 mm × 35 mm,
1152-pin FBGA)
KF40
(40 mm × 40 mm,
1517-pin FBGA)
NF40
(40 mm × 40 mm,
1517-pin FBGA)
3 V I/O LVDS I/O XCVR 3 V I/O LVDS I/O XCVR 3 V I/O LVDS I/O XCVR
SX 270 48 336 24
SX 320 48 336 24
SX 480 48 348 36
SX 570 48 348 36 96 600 36 48 540 48
SX 660 48 348 36 96 600 36 48 540 48
Related Information
I/O and High-Speed Differential I/O Interfaces in Intel Arria 10 Devices chapter, Intel
Arria 10 Device Handbook
Provides the number of 3 V and LVDS I/Os, and LVDS channels for each Intel Arria
10 device package.
Intel
®
Arria
®
10 Device Overview
A10-OVERVIEW | 2018.04.09
Intel
®
Arria
®
10 Device Overview
16
I/O Vertical Migration for Intel Arria 10 Devices
Figure 4. Migration Capability Across Intel Arria 10 Product Lines
The arrows indicate the migration paths. The devices included in each vertical migration path are shaded.
Devices with fewer resources in the same path have lighter shades.
To achieve the full I/O migration across product lines in the same migration path, restrict I/Os and
transceivers usage to match the product line with the lowest I/O and transceiver counts.
An LVDS I/O bank in the source device may be mapped to a 3 V I/O bank in the target device. To use
memory interface clock frequency higher than 533 MHz, assign external memory interface pins only to
banks that are LVDS I/O in both devices.
There may be nominal 0.15 mm package height difference between some product lines in the same
package type.
Some migration paths are not shown in the Intel Quartus Prime software Pin Migration View.
Note: To verify the pin migration compatibility, use the Pin Migration View window in the
Intel Quartus Prime software Pin Planner.
Adaptive Logic Module
Intel Arria 10 devices use a 20 nm ALM as the basic building block of the logic fabric.
The ALM architecture is the same as the previous generation FPGAs, allowing for
efficient implementation of logic functions and easy conversion of IP between the
device generations.
The ALM, as shown in following figure, uses an 8-input fracturable look-up table (LUT)
with four dedicated registers to help improve timing closure in register-rich designs
and achieve an even higher design packing capability than the traditional two-register
per LUT architecture.
Intel
®
Arria
®
10 Device Overview
A10-OVERVIEW | 2018.04.09
Intel
®
Arria
®
10 Device Overview
17
Figure 5. ALM for Intel Arria 10 Devices
FPGA Device
1
2
3
4
5
6
7
8
Adaptive
LUT
Full
Adder
Reg
Reg
Full
Adder
Reg
Reg
The Intel Quartus Prime software optimizes your design according to the ALM logic
structure and automatically maps legacy designs into the Intel Arria 10 ALM
architecture.
Variable-Precision DSP Block
The Intel Arria 10 variable precision DSP blocks support fixed-point arithmetic and
floating-point arithmetic.
Features for fixed-point arithmetic:
High-performance, power-optimized, and fully registered multiplication operations
18-bit and 27-bit word lengths
Two 18 x 19 multipliers or one 27 x 27 multiplier per DSP block
Built-in addition, subtraction, and 64-bit double accumulation register to combine
multiplication results
Cascading 19-bit or 27-bit when pre-adder is disabled and cascading 18-bit when
pre-adder is used to form the tap-delay line for filtering applications
Cascading 64-bit output bus to propagate output results from one block to the
next block without external logic support
Hard pre-adder supported in 19-bit and 27-bit modes for symmetric filters
Internal coefficient register bank in both 18-bit and 27-bit modes for filter
implementation
18-bit and 27-bit systolic finite impulse response (FIR) filters with distributed
output adder
Biased rounding support
Intel
®
Arria
®
10 Device Overview
A10-OVERVIEW | 2018.04.09
Intel
®
Arria
®
10 Device Overview
18

10AX090S2F45E1SG

Mfr. #:
Manufacturer:
Intel / Altera
Description:
FPGA - Field Programmable Gate Array
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union