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10AX090S2F45E1SG

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Table 20. Memory Standards Supported by the Hard Memory Controller
This table lists the overall capability of the hard memory controller. For specific details, refer to the External
Memory Interface Spec Estimator and Intel Arria 10 Device Datasheet.
Memory Standard Rate Support Ping Pong PHY Support Maximum Frequency
(MHz)
DDR4 SDRAM Quarter rate Yes 1,067
— 1,200
DDR3 SDRAM Half rate Yes 533
— 667
Quarter rate Yes 1,067
— 1,067
DDR3L SDRAM Half rate Yes 533
— 667
Quarter rate Yes 933
— 933
LPDDR3 SDRAM Half rate — 533
Quarter rate — 800
Table 21. Memory Standards Supported by the Soft Memory Controller
Memory Standard Rate Support Maximum Frequency
(MHz)
RLDRAM 3
(11)
Quarter rate 1,200
QDR IV SRAM
(11)
Quarter rate 1,067
QDR II SRAM Full rate 333
Half rate 633
QDR II+ SRAM Full rate 333
Half rate 633
QDR II+ Xtreme SRAM Full rate 333
Half rate 633
Table 22. Memory Standards Supported by the HPS Hard Memory Controller
The hard processor system (HPS) is available in Intel Arria 10 SoC devices only.
Memory Standard
Rate Support Maximum Frequency
(MHz)
DDR4 SDRAM Half rate 1,200
DDR3 SDRAM Half rate 1,067
DDR3L SDRAM Half rate 933
(11)
Intel Arria 10 devices support this external memory interface using hard PHY with soft
memory controller.
Intel
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Arria
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10 Device Overview
A10-OVERVIEW | 2018.04.09
Intel
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Arria
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25
Related Information
Intel Arria 10 Device Datasheet
Lists the memory interface performance according to memory interface standards,
rank or chip select configurations, and Intel Arria 10 device speed grades.
PCIe Gen1, Gen2, and Gen3 Hard IP
Intel Arria 10 devices contain PCIe hard IP that is designed for performance and
ease-of-use:
• Includes all layers of the PCIe stack—transaction, data link and physical layers.
• Supports PCIe Gen3, Gen2, and Gen1 Endpoint and Root Port in x1, x2, x4, or x8
lane configuration.
• Operates independently from the core logic—optional configuration via protocol
(CvP) allows the PCIe link to power up and complete link training in less than
100 ms while the Intel Arria 10 device completes loading the programming file for
the rest of the FPGA.
• Provides added functionality that makes it easier to support emerging features
such as Single Root I/O Virtualization (SR-IOV) and optional protocol extensions.
• Provides improved end-to-end datapath protection using ECC.
• Supports FPGA configuration via protocol (CvP) using PCIe at Gen3, Gen2, or
Gen1 speed.
Related Information
PCS Features on page 30
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet
Interlaken Support
The Intel Arria 10 enhanced PCS hard IP provides integrated Interlaken PCS
supporting rates up to 25.8 Gbps per lane.
The Interlaken PCS is based on the proven functionality of the PCS developed for
Intel’s previous generation FPGAs, which demonstrated interoperability with Interlaken
ASSP vendors and third-party IP suppliers. The Interlaken PCS is present in every
transceiver channel in Intel Arria 10 devices.
Related Information
PCS Features on page 30
10 Gbps Ethernet Support
The Intel Arria 10 enhanced PCS hard IP supports 10GBASE-R PCS compliant with
IEEE 802.3 10 Gbps Ethernet (10GbE). The integrated hard IP support for 10GbE and
the 10 Gbps transceivers save external PHY cost, board space, and system power.
Intel
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Arria
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10 Device Overview
A10-OVERVIEW | 2018.04.09
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Arria
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The scalable hard IP supports multiple independent 10GbE ports while using a single
PLL for all the 10GBASE-R PCS instantiations, which saves on core logic resources and
clock networks:
• Simplifies multiport 10GbE systems compared to XAUI interfaces that require an
external XAUI-to-10G PHY.
• Incorporates Electronic Dispersion Compensation (EDC), which enables direct
connection to standard 10 Gbps XFP and SFP+ pluggable optical modules.
• Supports backplane Ethernet applications and includes a hard 10GBASE-KR
Forward Error Correction (FEC) circuit that you can use for 10 Gbps and 40 Gbps
applications.
The 10 Gbps Ethernet PCS hard IP and 10GBASE-KR FEC are present in every
transceiver channel.
Related Information
PCS Features on page 30
Low Power Serial Transceivers
Intel Arria 10 FPGAs and SoCs include lowest power transceivers that deliver high
bandwidth, throughput and low latency.
Intel Arria 10 devices deliver the industry's lowest power consumption per transceiver
channel:
• 12.5 Gbps transceivers at as low as 242 mW
• 10 Gbps transceivers at as low as 168 mW
• 6 Gbps transceivers at as low as 117 mW
Intel Arria 10 transceivers support various data rates according to application:
• Chip-to-chip and chip-to-module applications—from 1 Gbps up to 25.8 Gbps
• Long reach and backplane applications—from 1 Gbps up to 12.5 with advanced
adaptive equalization
• Critical power sensitive applications—from 1 Gbps up to 11.3 Gbps using lower
power modes
The combination of 20 nm process technology and architectural advances provide the
following benefits:
• Significant reduction in die area and power consumption
• Increase of up to two times in transceiver I/O density compared to previous
generation devices while maintaining optimal signal integrity
• Up to 72 total transceiver channels—you can configure up to 6 of these channels
to run as fast as 25.8 Gbps
• All channels feature continuous data rate support up to the maximum rated speed
Intel
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Arria
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10 Device Overview
A10-OVERVIEW | 2018.04.09
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Arria
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10AX090S2F45E1SG

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Buy 10AX090S2F45E1SG
Manufacturer:
Intel / Altera
Description:
FPGA - Field Programmable Gate Array
Lifecycle:
New from this manufacturer.
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