Date Version Changes
August 2014 2014.08.18 • Updated Memory (Kb) M20K maximum resources for Arria 10 GX 660
devices from 42,660 to 42,620.
• Added GPIO columns consisting of LVDS I/O Bank and 3V I/O Bank in
the Package Plan table.
• Added how to use memory interface clock frequency higher than 533
MHz in the I/O vertical migration.
• Added information to clarify that RLDRAM3 support uses hard PHY with
soft memory controller.
• Added variable precision DSP blocks support for floating-point
arithmetic.
June 2014 2014.06.19 Updated number of dedicated I/Os in the HPS block to 17.
February 2014 2014.02.21 Updated transceiver speed grade options for GT devices in Figure 2.
February 2014 2014.02.06 Updated data rate for Arria 10 GT devices from 28.1 Gbps to 28.3 Gbps.
December 2013 2013.12.10 • Updated the HPS memory standards support from LPDDR2 to LPDDR3.
• Updated HPS block diagram to include dedicated HPS I/O and FPGA
Configuration blocks as well as repositioned SD/SDIO/MMC, DMA, SPI
and NAND Flash with ECC blocks .
December 2013 2013.12.02 Initial release.
Intel
®
Arria
®
10 Device Overview
A10-OVERVIEW | 2018.04.09
Intel
®
Arria
®
10 Device Overview
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