Table 6. Maximum Resource Counts for Intel Arria 10 GX Devices (GX 570, GX 660, GX
900, and GX 1150)
Resource Product Line
GX 570 GX 660 GX 900 GX 1150
Logic Elements (LE) (K) 570 660 900 1,150
ALM 217,080 251,680 339,620 427,200
Register 868,320 1,006,720 1,358,480 1,708,800
Memory (Kb) M20K 36,000 42,620 48,460 54,260
MLAB 5,096 5,788 9,386 12,984
Variable-precision DSP Block 1,523 1,687 1,518 1,518
18 x 19 Multiplier 3,046 3,374 3,036 3,036
PLL Fractional
Synthesis
16 16 32 32
I/O 16 16 16 16
17.4 Gbps Transceiver 48 48 96 96
GPIO
(3)
696 696 768 768
LVDS Pair
(4)
324 324 384 384
PCIe Hard IP Block 2 2 4 4
Hard Memory Controller 16 16 16 16
Package Plan
Table 7. Package Plan for Intel Arria 10 GX Devices (U19, F27, and F29)
Refer to I/O and High Speed I/O in Intel Arria 10 Devices chapter for the number of 3 V I/O, LVDS I/O, and
LVDS channels in each device package.
Product Line
U19
(19 mm × 19 mm,
484-pin UBGA)
F27
(27 mm × 27 mm,
672-pin FBGA)
F29
(29 mm × 29 mm,
780-pin FBGA)
3 V I/O LVDS I/O XCVR 3 V I/O LVDS I/O XCVR 3 V I/O LVDS I/O XCVR
GX 160 48 192 6 48 192 12 48 240 12
GX 220 48 192 6 48 192 12 48 240 12
GX 270 48 192 12 48 312 12
GX 320 48 192 12 48 312 12
GX 480 48 312 12
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Table 8. Package Plan for Intel Arria 10 GX Devices (F34, F35, NF40, and KF40)
Refer to I/O and High Speed I/O in Intel Arria 10 Devices chapter for the number of 3 V I/O, LVDS I/O, and
LVDS channels in each device package.
Product Line F34
(35 mm × 35 mm,
1152-pin FBGA)
F35
(35 mm × 35 mm,
1152-pin FBGA)
KF40
(40 mm × 40 mm,
1517-pin FBGA)
NF40
(40 mm × 40 mm,
1517-pin FBGA)
3 V
I/O
LVDS
I/O
XCVR 3 V
I/O
LVDS
I/O
XCVR 3 V
I/O
LVDS
I/O
XCVR 3 V
I/O
LVDS
I/O
XCVR
GX 270 48 336 24 48 336 24
GX 320 48 336 24 48 336 24
GX 480 48 444 24 48 348 36
GX 570 48 444 24 48 348 36 96 600 36 48 540 48
GX 660 48 444 24 48 348 36 96 600 36 48 540 48
GX 900 504 24 600 48
GX 1150 504 24 600 48
Table 9. Package Plan for Intel Arria 10 GX Devices (RF40, NF45, SF45, and UF45)
Refer to I/O and High Speed I/O in Intel Arria 10 Devices chapter for the number of 3 V I/O, LVDS I/O, and
LVDS channels in each device package.
Product Line
RF40
(40 mm × 40 mm,
1517-pin FBGA)
NF45
(45 mm × 45 mm)
1932-pin FBGA)
SF45
(45 mm × 45 mm)
1932-pin FBGA)
UF45
(45 mm × 45 mm)
1932-pin FBGA)
3 V
I/O
LVDS
I/O
XCVR 3 V
I/O
LVDS
I/O
XCVR 3 V
I/O
LVDS
I/O
XCVR 3 V
I/O
LVDS
I/O
XCVR
GX 900 342 66 768 48 624 72 480 96
GX 1150 342 66 768 48 624 72 480 96
Related Information
I/O and High-Speed Differential I/O Interfaces in Intel Arria 10 Devices chapter, Intel
Arria 10 Device Handbook
Provides the number of 3 V and LVDS I/Os, and LVDS channels for each Intel Arria
10 device package.
Intel Arria 10 GT
This section provides the available options, maximum resource counts, and package
plan for the Intel Arria 10 GT devices.
The information in this section is correct at the time of publication. For the latest
information and to get more details, refer to the Intel FPGA Product Selector.
Related Information
Intel FPGA Product Selector
Provides the latest information on Intel products.
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Available Options
Figure 2. Sample Ordering Code and Available Options for Intel Arria 10 GT Devices
Family Signature
Transceiver Count
Transceiver
Speed Grade
Package Type
Package Code
Operating Temperature
FPGA Fabric
Speed Grade
Optional Suffix
Indicates specific device
options or shipment method
T : GT variant
25.8 Gbps transceivers
10A : Intel Arria 10
090 : 900K logic elements
115 : 1,150K logic elements
S : 72
1 (fastest)
2
F : FineLine BGA (FBGA), 1.0 mm pitch
45
:
1,932 pins, 45 mm x 45 mm
E
:
1 (fastest)
2
3
Power Option
S
: Standard
RoHS
G : RoHS6
N : RoHS5
P : Leaded
ES : Engineering sample
10A
T
F
115
S
2
S
40
I
2
ESG
Logic Density
Family Variant
}
Contact Intel
for availability
Extended (T
J
= 0° C to 100° C)
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10AX115N2F45E2LG

Mfr. #:
Manufacturer:
Intel / Altera
Description:
FPGA - Field Programmable Gate Array
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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