Table 24. Improvements in 20 nm HPS
This table lists the key improvements of the 20 nm HPS compared to the 28 nm HPS.
Advantages/
Improvements
Description
Increased performance and
overdrive capability
While the nominal processor frequency is 1.2 GHz, the 20 nm HPS offers an “overdrive”
feature which enables a higher processor operating frequency. This requires a higher supply
voltage value that is unique to the HPS and may require a separate regulator.
Increased processor memory
bandwidth and DDR4
support
Up to 64-bit DDR4 memory at 2,400 Mbps support is available for the processor. The hard
memory controller for the HPS comprises a multi-port front end that manages connections
to a single port memory controller. The multi-port front end allows logic core and the HPS
to share ports and thereby the available bandwidth of the memory controller.
Flexible I/O sharing An advanced I/O pin muxing scheme allows improved sharing of I/O between the HPS and
the core logic. The following types of I/O are available for SoC:
17 dedicated I/Os—physically located inside the HPS block and are not accessible to
logic within the core. The 17 dedicated I/Os are used for HPS clock, resets, and
interfacing with boot devices, QSPI, and SD/MMC.
48 direct shared I/O—located closest to the HPS block and are ideal for high speed HPS
peripherals such as EMAC, USB, and others. There is one bank of 48 I/Os that supports
direct sharing where the 48 I/Os can be shared 12 I/Os at a time.
Standard (shared) I/O—all standard I/Os can be shared by the HPS peripherals and any
logic within the core. For designs where more than 48 I/Os are required to fully use all
the peripherals in the HPS, these I/Os can be connected through the core logic.
EMAC core Three EMAC cores are available in the HPS. The EMAC cores enable an application to
support two redundant Ethernet connections; for example, backplane, or two EMAC cores
for managing IEEE 1588 time stamp information while allowing a third EMAC core for debug
and configuration. All three EMACs can potentially share the same time stamps, simplifying
the 1588 time stamping implementation. A new serial time stamp interface allows core
logic to access and read the time stamp values. The integrated EMAC controllers can be
connected to external Ethernet PHY through the provided MDIO or I
2
C interface.
On-chip memory The on-chip memory is updated to 256 KB support and can support larger data sets and
real time algorithms.
ECC enhancements Improvements in L2 Cache ECC management allow identification of errors down to the
address level. ECC enhancements also enable improved error injection and status reporting
via the introduction of new memory mapped access to syndrome and data signals.
HPS to FPGA Interconnect
Backbone
Although the HPS and the Logic Core can operate independently, they are tightly coupled
via a high-bandwidth system interconnect built from high-performance ARM AMBA AXI bus
bridges. IP bus masters in the FPGA fabric have access to HPS bus slaves via the FPGA-to-
HPS interconnect. Similarly, HPS bus masters have access to bus slaves in the core fabric
via the HPS-to-FPGA bridge. Both bridges are AMBA AXI-3 compliant and support
simultaneous read and write transactions. Up to three masters within the core fabric can
share the HPS SDRAM controller with the processor. Additionally, the processor can be used
to configure the core fabric under program control via a dedicated 32-bit configuration port.
FPGA configuration and HPS
booting
The FPGA fabric and HPS in the SoCs are powered independently. You can reduce the clock
frequencies or gate the clocks to reduce dynamic power.
You can configure the FPGA fabric and boot the HPS independently, in any order, providing
you with more design flexibility.
Security New security features have been introduced for anti-tamper management, secure boot,
encryption (AES), and authentication (SHA).
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Features of the HPS
The HPS has the following features:
1.2-GHz, dual-core ARM Cortex-A9 MPCore processor with up to 1.5-GHz via
overdrive
ARMv7-A architecture that runs 32-bit ARM instructions, 16-bit and 32-bit
Thumb instructions, and 8-bit Java byte codes in Jazelle style
Superscalar, variable length, out-of-order pipeline with dynamic branch
prediction
Instruction Efficiency 2.5 MIPS/MHz, which provides total performance of 7500
MIPS at 1.5 GHz
Each processor core includes:
32 KB of L1 instruction cache, 32 KB of L1 data cache
Single- and double-precision floating-point unit and NEON media engine
CoreSight debug and trace technology
Snoop Control Unit (SCU) and Acceleration Coherency Port (ACP)
512 KB of shared L2 cache
256 KB of scratch RAM
Hard memory controller with support for DDR3, DDR4 and optional error
correction code (ECC) support
Multiport Front End (MPFE) Scheduler interface to the hard memory controller
8-channel direct memory access (DMA) controller
QSPI flash controller with SIO, DIO, QIO SPI Flash support
NAND flash controller (ONFI 1.0 or later) with DMA and ECC support, updated to
support 8 and 16-bit Flash devices and new command DMA to offload CPU for fast
power down recovery
Updated SD/SDIO/MMC controller to eMMC 4.5 with DMA with CE-ATA digital
command support
3 10/100/1000 Ethernet media access control (MAC) with DMA
2 USB On-the-Go (OTG) controllers with DMA
5 I
2
C controllers (3 can be used by EMAC for MIO to external PHY)
2 UART 16550 Compatible controllers
4 serial peripheral interfaces (SPI) (2 Master, 2 Slaves)
62 programmable general-purpose I/Os, which includes 48 direct share I/Os that
allows the HPS peripherals to connect directly to the FPGA I/Os
7 general-purpose timers
4 watchdog timers
Anti-tamper, Secure Boot, Encryption (AES) and Authentication (SHA)
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System Peripherals and Debug Access Port
Each Ethernet MAC, USB OTG, NAND flash controller, and SD/MMC controller module
has an integrated DMA controller. For modules without an integrated DMA controller,
an additional DMA controller module provides up to eight channels of high-bandwidth
data transfers. Peripherals that communicate off-chip are multiplexed with other
peripherals at the HPS pin level. This allows you to choose which peripherals interface
with other devices on your PCB.
The debug access port provides interfaces to industry standard JTAG debug probes
and supports ARM CoreSight debug and core traces to facilitate software development.
HPS–FPGA AXI Bridges
The HPS–FPGA bridges, which support the Advanced Microcontroller Bus Architecture
(AMBA) Advanced eXtensible Interface (AXI
) specifications, consist of the following
bridges:
FPGA-to-HPS AMBA AXI bridge—a high-performance bus supporting 32, 64, and
128 bit data widths that allows the FPGA fabric to issue transactions to slaves in
the HPS.
HPS-to-FPGA Avalon/AMBA AXI bridge—a high-performance bus supporting 32,
64, and 128 bit data widths that allows the HPS to issue transactions to slaves in
the FPGA fabric.
Lightweight HPS-to-FPGA AXI bridge—a lower latency 32 bit width bus that allows
the HPS to issue transactions to soft peripherals in the FPGA fabric. This bridge is
primarily used for control and status register (CSR) accesses to peripherals in the
FPGA fabric.
The HPS–FPGA AXI bridges allow masters in the FPGA fabric to communicate with
slaves in the HPS logic, and vice versa. For example, the HPS-to-FPGA AXI bridge
allows you to share memories instantiated in the FPGA fabric with one or both
microprocessors in the HPS, while the FPGA-to-HPS AXI bridge allows logic in the
FPGA fabric to access the memory and peripherals in the HPS.
Each HPS–FPGA bridge also provides asynchronous clock crossing for data transferred
between the FPGA fabric and the HPS.
HPS SDRAM Controller Subsystem
The HPS SDRAM controller subsystem contains a multiport SDRAM controller and DDR
PHY that are shared between the FPGA fabric (through the FPGA-to-HPS SDRAM
interface), the level 2 (L2) cache, and the level 3 (L3) system interconnect. The
FPGA-to-HPS SDRAM interface supports AMBA AXI and Avalon
®
Memory-Mapped
(Avalon-MM) interface standards, and provides up to six individual ports for access by
masters implemented in the FPGA fabric.
The HPS SDRAM controller supports up to 3 masters (command ports), 3x 64-bit read
data ports and 3x 64-bit write data ports.
To maximize memory performance, the SDRAM controller subsystem supports
command and data reordering, deficit round-robin arbitration with aging, and
high-priority bypass features.
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10AX115N2F45E2LG

Mfr. #:
Manufacturer:
Intel / Altera
Description:
FPGA - Field Programmable Gate Array
Lifecycle:
New from this manufacturer.
Delivery:
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