APA300-BG456I

ProASIC
PLUS
Flash Family FPGAs
v5.9 1-3
Live at Power-Up
The Actel flash-based ProASIC
PLUS
devices support
Level 0 of the live at power-up (LAPU) classification
standard. This feature helps in system component
initialization, executing critical tasks before the
processor wakes up, setting up and configuring memory
blocks, clock generation, and bus activity management.
The LAPU feature of flash-based ProASIC
PLUS
devices
greatly simplifies total system design and reduces total
system cost, often eliminating the need for complex
programmable logic device (CPLD) and clock generation
PLLs that are used for this purpose in a system. In
addition, glitches and brownouts in system power will
not corrupt the ProASIC
PLUS
device's flash configuration,
and unlike SRAM-based FPGAs, the device will not have
to be reloaded when system power is restored. This
enables the reduction or complete removal of the
configuration PROM, expensive voltage monitor,
brownout detection, and clock generator devices from
the PCB design. Flash-based ProASIC
PLUS
devices simplify
total system design, and reduce cost and design risk,
while increasing system reliability and improving system
initialization time.
Flash Switch
Unlike SRAM FPGAs, ProASIC
PLUS
uses a live-at-power-up
ISP flash switch as its programming element.
In the ProASIC
PLUS
flash switch, two transistors share the
floating gate, which stores the programming
information. One is the sensing transistor, which is only
used for writing and verification of the floating gate
voltage. The other is the switching transistor. It can be
used in the architecture to connect/separate routing nets
or to configure logic. It is also used to erase the floating
gate (Figure 1-2 on page 1-2).
Logic Tile
The logic tile cell (Figure 1-3) has three inputs (any or all
of which can be inverted) and one output (which can
connect to both ultra-fast local and efficient long-line
routing resources). Any three-input, one-output logic
function (except a three-input XOR) can be configured as
one tile. The tile can be configured as a latch with clear
or set or as a flip-flop with clear or set. Thus, the tiles can
flexibly map logic and sequential gates of a design.
Figure 1-3 Core Logic Tile
Local Routing
In 1
In 2 (CLK)
In 3 (Reset)
Efficient Long-Line Routing
ProASIC
PLUS
Flash Family FPGAs
1-4 v5.9
Data Sheet Categories
In order to provide the latest information to designers, some datasheets are published before data has been fully
characterized. Datasheets are designated as "Product Brief," "Advanced," "Production," and "Datasheet
Supplement." The definition of these categories are as follows:
Product Brief
The product brief is a summarized version of a datasheet (advanced or production) containing general product
information. This brief gives an overview of specific device and family information.
Advance
This datasheet version contains initial estimated information based on simulation, other products, devices, or speed
grades. This information can be used as estimates, but not for production.
Unmarked (production)
This datasheet version contains information that is considered to be final.
Datasheet Supplement
The datasheet supplement gives specific device information for a derivative family that differs from the general family
datasheet. The supplement is to be used in conjunction with the datasheet to obtain more detailed information and
for specifications that do not differ between the two families.
Export Administration Regulations (EAR)
The products described in this datasheet are subject to the Export Administration Regulations (EAR). They could
require an approved export license prior to export from the United States. An export includes release of product or
disclosure of technology to a foreign national inside or outside the United States.
Actel Safety Critical, Life Support, and High-Reliability Applications
Policy
The Actel products described in this advance status datasheet may not have completed Actel’s qualification process.
Actel may amend or enhance products during the product introduction and qualification process, resulting in changes
in device functionality or performance. It is the responsibility of each customer to ensure the fitness of any Actel
product (but especially a new product) for a particular purpose, including appropriateness for safety-critical, life-
support, and other high-reliability applications. Consult Actel’s Terms and Conditions for specific liability exclusions
relating to life-support applications. A reliability report covering all of Actel’s products is available on the Actel
website at http://www.actel.com/documents/ORT_Report.pdf. Actel also offers a variety of enhanced qualification and
lot acceptance screening procedures. Contact your local Actel sales office for additional reliability information.

APA300-BG456I

Mfr. #:
Manufacturer:
Microchip / Microsemi
Description:
FPGA - Field Programmable Gate Array ProASIC Plus
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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