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SST39WF1601-70-4I-MAQE-T

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35
©2013 Silicon Storage Technology, Inc. DS-20005014B 11/2013
7
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
Block-Erase operation are ignored. When WP# is low, any attempt to Sector- (Block-) Erase the pro-
tected block will be ignored. During the command sequence, WP# should be statically held high or low.
Erase-Suspend/Erase-Resume Commands
The Erase-Suspend operation temporarily suspends a Sector- or Block-Erase operation thus allowing
data to be read from any memory location, or program data into any sector/block that is not suspended
for an Erase operation. The operation is executed by issuing one byte command sequence with Erase-
Suspend command (B0H). The device automatically enters read mode typically within 20 µs after the
Erase-Suspend command had been issued. Valid data can be read from any sector or block that is not
suspended from an Erase operation. Reading at address location within erase-suspended sectors/
blocks will output DQ
2
toggling and DQ
6
at “1”. While in Erase-Suspend mode, a Word-Program oper-
ation is allowed except for the sector or block selected for Erase-Suspend.
To resume Sector-Erase or Block-Erase operation which has been suspended the system must issue
Erase Resume command. The operation is executed by issuing one byte command sequence with
Erase Resume command (30H) at any address in the last Byte sequence.
Chip-Erase Operation
The SST39WF1601/1602 provide a Chip-Erase operation, which allows the user to erase the entire
memory array to the “1” state. This is useful when the entire device must be quickly erased.
The Chip-Erase operation is initiated by executing a six-byte command sequence with Chip-Erase
command (10H) at address 5555H in the last byte sequence. The Erase operation begins with the ris-
ing edge of the sixth WE# or CE#, whichever occurs first. During the Erase operation, the only valid
read is Toggle Bit or Data# Polling. See Table 6 for the command sequence, Figure 10 for timing dia-
gram, and Figure 24 for the flowchart. Any commands issued during the Chip-Erase operation are
ignored. When WP# is low, any attempt to Chip-Erase will be ignored. During the command sequence,
WP# should be statically held high or low.
Write Operation Status Detection
The SST39WF1601/1602 provide two software means to detect the completion of a Write (Program or
Erase) cycle, in order to optimize the system write cycle time. The software detection includes two sta-
tus bits: Data# Polling (DQ
7
) and Toggle Bit (DQ
6
). The End-of-Write detection mode is enabled after
the rising edge of WE#, which initiates the internal Program or Erase operation.
The actual completion of the nonvolatile write is asynchronous with the system; therefore, either a
Data# Polling or Toggle Bit read may be simultaneous with the completion of the write cycle. If this
occurs, the system may possibly get an erroneous result, i.e., valid data may appear to conflict with
either DQ
7
or DQ
6
. In order to prevent spurious rejection, if an erroneous result occurs, the software
routine should include a loop to read the accessed location an additional two (2) times. If both reads
are valid, then the device has completed the Write cycle, otherwise the rejection is valid.
©2013 Silicon Storage Technology, Inc. DS-20005014B 11/2013
8
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
Data# Polling (DQ
7
)
When the SST39WF1601/1602 are in the internal Program operation, any attempt to read DQ
7
will
produce the complement of the true data. Once the Program operation is completed, DQ
7
will produce
true data. Note that even though DQ
7
may have valid data immediately following the completion of an internal
Write operation, the remaining data outputs may still be invalid: valid data on the entire data bus will appear in
subsequent successive Read cycles after an interval of 1 µs. During internal Erase operation, any attempt
to read DQ
7
will produce a ‘0’. Once the internal Erase operation is completed, DQ
7
will produce a ‘1’.
The Data# Polling is valid after the rising edge of fourth WE# (or CE#) pulse for Program operation. For
Sector-, Block- or Chip-Erase, the Data# Polling is valid after the rising edge of sixth WE# (or CE#)
pulse. See Figure 7 for Data# Polling timing diagram and Figure 21 for a flowchart.
Toggle Bits (DQ6 and DQ2)
During the internal Program or Erase operation, any consecutive attempts to read DQ
6
will produce
alternating “1”s and “0”s, i.e., toggling between 1 and 0. When the internal Program or Erase operation
is completed, the DQ
6
bit will stop toggling. The device is then ready for the next operation. For Sector-
, Block-, or Chip-Erase, the toggle bit (DQ
6
) is valid after the rising edge of sixth WE# (or CE#) pulse.
DQ
6
will be set to “1” if a Read operation is attempted on an Erase-Suspended Sector/Block. If Pro-
gram operation is initiated in a sector/block not selected in Erase-Suspend mode, DQ
6
will toggle.
An additional Toggle Bit is available on DQ
2
, which can be used in conjunction with DQ
6
to check
whether a particular sector is being actively erased or erase-suspended. Table 2 shows detailed status
bits information. The Toggle Bit (DQ
2
) is valid after the rising edge of the last WE# (or CE#) pulse of
Write operation. See Figure 8 for Toggle Bit timing diagram and Figure 21 for a flowchart.
Note: DQ
7
and DQ
2
require a valid address when reading status information.
Table 2: Write Operation Status
Status DQ
7
DQ
6
DQ
2
Normal Operation Standard Program DQ
7
# Toggle No Toggle
Standard Erase 0 Toggle Toggle
Erase-Suspend
Mode
Read from Erase-Suspended Sector/Block 1 1 Toggle
Read from Non- Erase-Suspended Sector/Block Data Data Data
Program DQ
7
# Toggle N/A
T2.0 20005014
©2013 Silicon Storage Technology, Inc. DS-20005014B 11/2013
9
16 Mbit Multi-Purpose Flash Plus
SST39WF1601 / SST39WF1602
Data Sheet
Data Protection
The SST39WF1601/1602 provide both hardware and software features to protect nonvolatile data from
inadvertent writes.
Hardware Data Protection
Noise/Glitch Protection: A WE# or CE# pulse of less than 5 ns will not initiate a write cycle.
V
DD
Power Up/Down Detection: The Write operation is inhibited when V
DD
is less than 1.5V.
Write Inhibit Mode: Forcing OE# low, CE# high, or WE# high will inhibit the Write operation. This pre-
vents inadvertent writes during power-up or power-down.
Hardware Block Protection
The SST39WF1602 support top hardware block protection, which protects the top 32 KWord block of
the device. The SST39WF1601 support bottom hardware block protection, which protects the bottom
32 KWord block of the device. The Boot Block address ranges are described in Table 3. Program and
Erase operations are prevented on the 32 KWord when WP# is low. If WP# is left floating, it is internally
held high via a pull-up resistor, and the Boot Block is unprotected, enabling Program and Erase opera-
tions on that block.
Hardware Reset (RST#)
The RST# pin provides a hardware method of resetting the device to read array data. When the RST#
pin is held low for at least T
RP,
any in-progress operation will terminate and return to Read mode. When
no internal Program/Erase operation is in progress, a minimum period of T
RHR
is required after RST#
is driven high before a valid Read can take place (see Figure 16).
The Erase or Program operation that has been interrupted needs to be reinitiated after the device
resumes normal operation mode to ensure data integrity.
Software Data Protection (SDP)
The SST39WF1601/1602 provide the JEDEC approved Software Data Protection scheme for all data
alteration operations, i.e., Program and Erase. Any Program operation requires the inclusion of the
three-byte sequence. The three-byte load sequence is used to initiate the Program operation, provid-
ing optimal protection from inadvertent Write operations, e.g., during the system power-up or power-
down. Any Erase operation requires the inclusion of six-byte sequence. These devices are shipped
with the Software Data Protection permanently enabled. See Table 6 for the specific software com-
mand codes. During SDP command sequence, invalid commands will abort the device to read mode
within T
RC.
The contents of DQ
15
-DQ
8
can be V
IL
or V
IH
, but no other value, during any SDP command
sequence.
Table 3: Boot Block Address Ranges
Product Address Range
Bottom Boot Block
SST39WF1601 000000H-007FFFH
Top Boot Block
SST39WF1602 0F8000H-0FFFFFH
T3.0 20005014
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P35

SST39WF1601-70-4I-MAQE-T

Mfr. #:
Buy SST39WF1601-70-4I-MAQE-T
Manufacturer:
Microchip Technology
Description:
NOR Flash 1.65V to 1.95V 16Mbit Multi-Prps Fl
Lifecycle:
New from this manufacturer.
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