ADuM3300/ADuM3301 Data Sheet
Rev. D | Page 4 of 20
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM3300BRWZ/ADuM3301BRWZ
Minimum Pulse Width
2
PW 100 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
10 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
20 32 50 ns C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |t
PLH
− t
PHL
|
4
PWD
3
ns
C
L
= 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
15 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels
6
t
PSKCD
3 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels
6
t
PSKOD
6 ns C
L
= 15 pF, CMOS signal levels
ADuM3300CRWZ/ADuM3301CRWZ
Minimum Pulse Width
2
PW 8.3 11.1 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
90 120 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
18 27 32 ns C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |t
PLH
− t
PHL
|
4
PWD 0.5 2 ns C
L
= 15 pF, CMOS signal levels
Change vs. Temperature 3 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
10 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels
6
t
PSKCD
2 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels
6
t
PSKOD
5 ns C
L
= 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
t
PHZ
, t
PLH
6 8 ns C
L
= 15 pF, CMOS signal levels
Output Enable Propagation Delay
(High Impedance-to-High/Low)
t
PZH
, t
PZL
6 8 ns C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) t
R
/t
F
2.5 ns C
L
= 15 pF, CMOS signal levels
Common-Mode Transient Immunity
at Logic High Output
7
|CM
H
| 25 35 kV/µs V
Ix
= V
DD1
or V
DD2
, V
CM
= 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity
at Logic Low Output
7
|CM
L
| 25 35 kV/µs V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
Refresh Rate f
r
1.2 Mbps
Input Dynamic Supply Current per Channel
8
I
DDI (D)
0.20 mA/Mbps
Output Dynamic Supply Current per Channel
8
I
DDO (D)
0.05 mA/Mbps
1
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through
Figure 12 for total V
DD1
and V
DD2
supply currents as a function of data rate for ADuM3300/ADuM3301 channel configurations.
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
t
PHL
propagation delay is measured from the 50% level of the falling edge of the V
Ix
signal to the 50% level of the falling edge of the V
Ox
signal. t
PLH
propagation delay is
measured from the 50% level of the rising edge of the V
Ix
signal to the 50% level of the rising edge of the V
Ox
signal.
5
t
PSK
is the magnitude of the worst-case difference in t
PHL
or t
PLH
that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. CM
L
is the maximum common-mode voltage slew rate
that can be sustained while maintaining V
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.
Data Sheet ADuM3300/ADuM3301
Rev. D | Page 5 of 20
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All voltages are relative to their respective ground. 3.0 V ≤ V
DD1
≤ 3.6 V, 3.0 V ≤ V
DD2
≤ 3.6 V; all minimum/maximum specifications apply
over the entire recommended operation range, unless otherwise noted; all typical specifications are at T
A
= 25°C, V
DD1
= V
DD2
= 3.3 V.
Table 2.
Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS
Input Supply Current per Channel, Quiescent I
DDI (Q)
0.37 0.57 mA
Output Supply Current per Channel, Quiescent I
DDO (Q)
0.25 0.37 mA
ADuM3300, Total Supply Current, Four Channels
1
DC to 2 Mbps
V
DD1
Supply Current I
DD1 (Q)
1.4 1.9 mA DC to 1 MHz logic signal freq.
V
DD2
Supply Current I
DD2 (Q)
0.7 1.2 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
V
DD1
Supply Current I
DD1 (10)
3.8 5.3 mA 5 MHz logic signal freq.
V
DD2
Supply Current I
DD2 (10)
1.5 2.1 mA 5 MHz logic signal freq.
V
DD1
Supply Current I
DD1 (90)
28 41 mA 45 MHz logic signal freq.
V
DD2
Supply Current I
DD2 (90)
8.2 11 mA 45 MHz logic signal freq.
ADuM3301, Total Supply Current, Four Channels
1
DC to 2 Mbps
V
DD1
Supply Current I
DD1 (Q)
1.1 1.6 mA DC to 1 MHz logic signal freq.
V
DD2
Supply Current I
DD2 (Q)
0.9 1.4 mA DC to 1 MHz logic signal freq.
10 Mbps (BRW and CRW Grades Only)
V
DD1
Supply Current I
DD1 (10)
3.0 4.1 mA 5 MHz logic signal freq.
V
DD2
Supply Current I
DD2 (10)
2.2 2.9 mA 5 MHz logic signal freq.
90 Mbps (CRW Grade Only)
V
DD1
Supply Current I
DD1 (90)
22 31 mA 45 MHz logic signal freq.
V
DD2
Supply Current I
DD2 (90)
15 21 mA 45 MHz logic signal freq.
For All Models
Input Currents I
IA
, I
IB
, I
IC
,
I
ID
, I
E1
, I
E2
−10 +0.01 +10 µA 0 V ≤ V
IA
, V
IB
, V
IC
, V
ID
≤ V
DD1
or V
DD2
,
0 V ≤ V
E1
,V
E2
≤ V
DD1
or V
DD2
Logic High Input Threshold
V
IH
, V
EH
1.6 V
Logic Low Input Threshold
V
IL
, V
EL
0.4 V
Logic High Output Voltages V
OAH
, V
OBH
,
V
OCH
, V
ODH
(V
DD1
or
V
DD2
) − 0.1
3.0 V I
Ox
= −20 µA, V
Ix
= V
IxH
(V
DD1
or
V
DD2
) − 0.4
2.8 V I
Ox
= −4 mA, V
Ix
= V
IxH
V
OAL
, V
OBL
,
V
OCL
, V
ODL
0.0
0.1
V
I
Ox
= 20 µA, V
Ix
= V
IxL
0.04 0.1 V I
Ox
= 400 µA, V
Ix
= V
IxL
0.2 0.4 V I
Ox
= 4 mA, V
Ix
= V
IxL
SWITCHING SPECIFICATIONS
ADuM3300AWRZ/ADuM3301ARWZ
Minimum Pulse Width
2
PW 1000 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
1 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
50 75 100 ns C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |t
PLH
− t
PHL
|
4
PWD 40 ns C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
50 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching
6
t
PSKCD/OD
50 ns C
L
= 15 pF, CMOS signal levels
ADuM3300/ADuM3301 Data Sheet
Rev. D | Page 6 of 20
Parameter Symbol Min Typ Max Unit Test Conditions
ADuM3300BRWZ/ADuM3301BRWZ
Minimum Pulse Width
2
PW 100 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
10 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
20 38 50 ns C
L
= 15 pF, CMOS signal levels
PLH
PHL
4
PWD
3
ns
C
L
= 15 pF, CMOS signal levels
Change vs. Temperature 5 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
22 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels
6
t
PSKCD
3 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels
6
t
PSKOD
6 ns C
L
= 15 pF, CMOS signal levels
ADuM3300CRWZ/ADuM3301CRWZ
Minimum Pulse Width
2
PW 8.3 11.1 ns C
L
= 15 pF, CMOS signal levels
Maximum Data Rate
3
90 120 Mbps C
L
= 15 pF, CMOS signal levels
Propagation Delay
4
t
PHL
, t
PLH
20 34 45 ns C
L
= 15 pF, CMOS signal levels
Pulse Width Distortion, |t
PLH
− t
PHL
|
4
PWD 0.5 2 ns C
L
= 15 pF, CMOS signal levels
Change vs. Temperature 3 ps/°C C
L
= 15 pF, CMOS signal levels
Propagation Delay Skew
5
t
PSK
16 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Codirectional Channels
6
t
PSKCD
2 ns C
L
= 15 pF, CMOS signal levels
Channel-to-Channel Matching,
Opposing-Directional Channels
6
t
PSKOD
5 ns C
L
= 15 pF, CMOS signal levels
For All Models
Output Disable Propagation Delay
(High/Low-to-High Impedance)
t
PHZ
, t
PLH
6 8 ns C
L
= 15 pF, CMOS signal levels
Output Enable Propagation Delay
(High Impedance-to-High/Low)
t
PZH
, t
PZL
6 8 ns C
L
= 15 pF, CMOS signal levels
Output Rise/Fall Time (10% to 90%) t
R
/t
F
3 ns C
L
= 15 pF, CMOS signal levels
Common-Mode Transient Immunity
at Logic High Output
7
|CM
H
| 25 35 kV/µs V
Ix
= V
DD1
or V
DD2
, V
CM
= 1000 V,
transient magnitude = 800 V
Common-Mode Transient Immunity
at Logic Low Output
7
|CM
L
| 25 35 kV/µs V
Ix
= 0 V, V
CM
= 1000 V,
transient magnitude = 800 V
Refresh Rate f
r
1.1 Mbps
Input Dynamic Supply Current per Channel
8
I
DDI (D)
0.10 mA/Mbps
Output Dynamic Supply Current per Channel
8
I
DDO (D)
0.03 mA/Mbps
1
The supply current values for all four channels are combined when running at identical data rates. Output supply current values are specified with no output load
present. The supply current associated with an individual channel operating at a given data rate can be calculated as described in the Power Consumption section.
See Figure 6 through Figure 8 for information on per-channel supply current as a function of data rate for unloaded and loaded conditions. See Figure 9 through
Figure 12 for total V
DD1
and V
DD2
supply currents as a function of data rate for ADuM3300/ADuM3301 channel configurations.
2
The minimum pulse width is the shortest pulse width at which the specified pulse width distortion is guaranteed.
3
The maximum data rate is the fastest data rate at which the specified pulse width distortion is guaranteed.
4
t
PHL
propagation delay is measured from the 50% level of the falling edge of the V
Ix
signal to the 50% level of the falling edge of the V
Ox
signal. t
PLH
propagation delay is
measured from the 50% level of the rising edge of the V
Ix
signal to the 50% level of the rising edge of the V
Ox
signal.
5
t
PSK
is the magnitude of the worst-case difference in t
PHL
or t
PLH
that is measured between units at the same operating temperature, supply voltages, and output load
within the recommended operating conditions.
6
Codirectional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of
the isolation barrier. Opposing-directional channel-to-channel matching is the absolute value of the difference in propagation delays between any two channels with
inputs on opposing sides of the isolation barrier.
7
CM
H
is the maximum common-mode voltage slew rate that can be sustained while maintaining V
O
> 0.8 V
DD2
. CM
L
is the maximum common-mode voltage slew rate
that can be sustained while maintaining V
O
< 0.8 V. The common-mode voltage slew rates apply to both rising and falling common-mode voltage edges. The transient
magnitude is the range over which the common mode is slewed.
8
Dynamic supply current is the incremental amount of supply current required for a 1 Mbps increase in signal data rate. See Figure 6 through Figure 8 for information
on per-channel supply current for unloaded and loaded conditions. See the Power Consumption section for guidance on calculating the per-channel supply current
for a given data rate.

ADUM3300BRWZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital Isolators Triple-CH Digital EH System-Level ESD
Lifecycle:
New from this manufacturer.
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