DS026 (v3.9) November 18, 2002 www.xilinx.com 1
Product Specification 1-800-255-7778
© 2001, 2002 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and further disclaimers are as listed at http://www.xilinx.com/legal.htm. All
other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
NOTICE OF DISCLAIMER: Xilinx is providing this design, code, or information "as is." By providing the design, code, or information as one possible implementation of this feature,
application, or standard, Xilinx makes no representation that this implementation is free from any claims of infringement. You are responsible for obtaining any rights you may
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Features
In-system programmable 3.3V PROMs for
configuration of Xilinx FPGAs
- Endurance of 20,000 program/erase cycles
- Program/erase over full commercial/industrial
voltage and temperature range
IEEE Std 1149.1 boundary-scan (JTAG) support
Simple interface to the FPGA
Cascadable for storing longer or multiple bitstreams
Low-power advanced CMOS FLASH process
Dual configuration modes
- Serial Slow/Fast configuration (up to 33 MHz)
- Parallel (up to 264 Mb/s at 33 MHz)
5V tolerant I/O pins accept 5V, 3.3V and 2.5V signals
3.3V or 2.5V output capability
Available in PC20, SO20, PC44 and VQ44 packages
Design support using the Xilinx Alliance and
Foundation series software packages.
JTAG command initiation of standard FPGA
configuration
Description
Xilinx introduces the XC18V00 series of in-system program-
mable configuration PROMs (Figure 1). Initial devices in this
3.3V family are a 4-megabit, a 2-megabit, a 1-megabit, a
512-Kbit, and a 256-Kbit PROM that provide an
easy-to-use, cost-effective method for re-programming and
storing large Xilinx FPGA or CPLD configuration bitstreams.
When the FPGA is in Master Serial mode, it generates a
configuration clock that drives the PROM. A short access
time after CE
and OE are enabled, data is available on the
PROM DATA (D0) pin that is connected to the FPGA D
IN
pin. New data is available a short access time after each ris-
ing clock edge. The FPGA generates the appropriate num-
ber of clock pulses to complete the configuration. When the
FPGA is in Slave Serial mode, the PROM and the FPGA are
clocked by an external clock.
When the FPGA is in Master-SelectMAP mode, the FPGA
generates a configuration clock that drives the PROM.
When the FPGA is in Slave-Parallel or Slave-SelectMAP
Mode, an external oscillator generates the configuration
clock that drives the PROM and the FPGA. After CE
and OE
are enabled, data is available on the PROMs DATA (D0-D7)
pins. New data is available a short access time after each
rising clock edge. The data is clocked into the FPGA on the
following rising edge of the CCLK. Neither Slave-Parallel
nor SelectMAP utilize a Length Count, so a free-running
oscillator can be used in the Slave-Parallel or Slave-
SelecMAP modes.
Multiple devices can be concatenated by using the CEO
output to drive the CE input of the following device. The
clock inputs and the DATA outputs of all PROMs in this
chain are interconnected. All devices are compatible and
can be cascaded with other members of the family or with
the XC17V00 one-time programmable Serial PROM family.
0
XC18V00 Series In-System
Programmable Configuration
PROMs
DS026 (v3.9) November 18, 2002
00
Product Specification
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XC18V00 Series In-System Programmable Configuration PROMs
2 www.xilinx.com DS026 (v3.9) November 18, 2002
1-800-255-7778 Product Specification
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Pinout and Pin Description
Pins not listed are "no connects."
Figure 1: XC18V00 Series Block Diagram
Control
and
JTAG
Interface
Memory
Serial
or
Parallel
Interface
D0 DATA
Serial or Parallel Mode
D[1:7]
Parallel Interface
Data
Address
CLK
CE
TCK
TMS
TDI
TDO
OE/Reset
CEO
Data
DS026_01_090502
7
CF
Table 1: Pin Names and Descriptions
Pin
Name
Boundary
Scan
Order Function Pin Description
44-pin
VQFP
44-pin
PLCC
20-pin
SOIC &
PLCC
D0 4 DATA OUT D0 is the DATA output pin to provide data for
configuring an FPGA in serial mode.
40 2 1
3OUTPUT
ENABLE
D1 6 DATA OUT D0-D7 are the output pins to provide parallel
data for configuring a Xilinx FPGA in
Slave-Parallel/SelectMap mode.
29 35 16
5OUTPUT
ENABLE
D2 2 DATA OUT 42 4 2
1OUTPUT
ENABLE
D3 8 DATA OUT 27 33 15
7OUTPUT
ENABLE
D4 24 DATA OUT 9 15 7
(1)
23 OUTPUT
ENABLE
D5 10 DATA OUT 25 31 14
9OUTPUT
ENABLE
D6 17 DATA OUT 14 20 9
16 OUTPUT
ENABLE
D7 14 DATA OUT 19 25 12
13 OUTPUT
ENABLE
XC18V00 Series In-System Programmable Configuration PROMs
DS026 (v3.9) November 18, 2002 www.xilinx.com 3
Product Specification 1-800-255-7778
R
CLK 0 DATA IN Each rising edge on the CLK input increments
the internal address counter if both CE
is Low
and OE/RESET
is High.
43 5 3
OE/
RESET
20 DATA IN When Low, this input holds the address
counter reset and the DATA output is in a
high-impedance state. This is a bidirectional
open-drain pin that is held Low while the
PROM is reset. Polarity is NOT
programmable.
13 19 8
19 DATA OUT
18 OUTPUT
ENABLE
CE
15 DATA IN When CE is High, the device is put into
low-power standby mode, the address
counter is reset, and the DATA pins are put in
a high-impedance state.
15 21 10
CF
22 DATA OUT Allows JTAG CONFIG instruction to initiate
FPGA configuration without powering down
FPGA. This is an open-drain output that is
pulsed Low by the JTAG CONFIG command.
10 16 7
(1)
21 OUTPUT
ENABLE
CEO
12 DATA OUT Chip Enable Output (CEO) is connected to
the CE
input of the next PROM in the chain.
This output is Low when CE
is Low and
OE/RESET
input is High, AND the internal
address counter has been incremented
beyond its Terminal Count (TC) value. CEO
returns to High when OE/RESET
goes Low or
CE
goes High.
21 27 13
11 OUTPUT
ENABLE
GND GND is the ground connection. 6, 18, 28 &
41
3, 12, 24
& 34
11
TMS MODE
SELECT
The state of TMS on the rising edge of TCK
determines the state transitions at the Test
Access Port (TAP) controller. TMS has an
internal 50K ohm resistive pull-up on it to
provide a logic 1 to the device if the pin is not
driven.
5115
TCK CLOCK This pin is the JTAG test clock. It sequences
the TAP controller and all the JTAG test and
programming electronics.
7136
TDI DATA IN This pin is the serial input to all JTAG
instruction and data registers. TDI has an
internal 50K ohm resistive pull-up on it to
provide a logic 1 to the system if the pin is
not driven.
394
TDO DATA OUT This pin is the serial output for all JTAG
instruction and data registers. TDO has an
internal 50K ohm resistive pull-up on it to
provide a logic 1 to the system if the pin is
not driven.
31 37 17
V
CC
Positive 3.3V supply voltage for internal logic
and input buffers.
17, 35 &
38
23, 41 &
44
18 & 20
Table 1: Pin Names and Descriptions (Continued)
Pin
Name
Boundary
Scan
Order Function Pin Description
44-pin
VQFP
44-pin
PLCC
20-pin
SOIC &
PLCC

XC18V256PC20C

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Xilinx
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