72V01L25JGI8

1
JUNE 2012
3.3 VOLT CMOS ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9,
2,048 x 9, 4,096 x 9,
8,192 x 9, 16,384 x 9
IDT72V01, IDT72V02
IDT72V03, IDT72V04
IDT72V05, IDT72V06
IDT and the IDT logo are trademarks of Integrated Device Technology, Inc
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
©2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-3033/7
FEATURES:
3.3V family uses less power than the 5 Volt 7201/7202/7203/7204/
7205/7206 family
512 x 9 organization (72V01)
1,024 x 9 organization (72V02)
2,048 x 9 organization (72V03)
4,096 X 9 organization (72V04)
8,192 x 9 organization (72V05)
16,384 X 9 organization (72V06)
Functionally compatible with 720x family
Low-power consumption
— Active: 180 mW (max.)
— Power-down: 18 mW (max.)
15 ns access time
Asynchronous and simultaneous read and write
Fully expandable by both word depth and/or bit width
Status Flags: Empty, Half-Full, Full
Auto-retransmit capability
Available in 32-pin PLCC
Industrial temperature range (–40
°°
°°
°
C to +85
°°
°°
°
C) is available
Green parts available, see ordering information
FUNCTIONAL BLOCK DIAGRAM
W
WRITE
CONTROL
READ
CONTROL
R
FLAG
LOGIC
EXPANSION
LOGIC
XI
WRITE
POINTER
RAM
ARRAY
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
16,384 x 9
READ
POINTER
DATA INPUTS
RESET
LOGIC
THREE-
STATE
BUFFERS
DATA OUTPUTS
EF
FF
XO/HF
RS
FL/RT
(D
0-
D
8
)
3033 drw 01
(Q
0-
Q
8
)
DESCRIPTION:
The IDT72V01/72V02/72V03/72V04/72V05/72V06 are dual-port FIFO
memories that operate at a power supply voltage (Vcc) between 3.0V and 3.6V.
Their architecture, functional operation and pin assignments are identical to
those of the IDT7201/7202/7203/7204/7205/7206. These devices load and
empty data on a first-in/first-out basis. They use Full and Empty flags to prevent
data overflow and underflow and expansion logic to allow for unlimited
expansion capability in both word size and depth.
The reads and writes are internally sequential through the use of ring
pointers, with no address information required to load and unload data. Data
is toggled in and out of the devices through the use of the Write (W) and Read
(R) pins. The devices have a maximum data access time as fast as 25 ns.
The devices utilize a 9-bit wide data array to allow for control and parity bits
at the user’s option. This feature is especially useful in data communications
applications where it is necessary to use a parity bit for transmission/reception
error checking. They also feature a Retransmit (RT) capability that allows for
reset of the read pointer to its initial position when RT is pulsed LOW to allow for
retransmission from the beginning of data. A Half-Full Flag is available in the
single device mode and width expansion modes.
These FIFOs are fabricated using high-speed CMOS technology. It has
been designed for those applications requiring asynchronous and simultane-
ous read/writes in multiprocessing and rate buffer applications.
2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V01/72V02/72V03/72V04/72V05/72V06 3.3V ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 and 16,384 x 9
PIN CONFIGURATION
IDT72V01
IDT72V02
IDT72V03 IDT72V05
IDT72V04 IDT72V06
Commercial & Industrial
(1)
Commercial & Industrial
(1)
tA = 15, 25, 35 ns tA = 15, 25, 35 ns
Symbol Parameter Min. Max. Min. Max. Unit
ILI
(2)
Input Leakage Current (Any Input) 1 1 1 1 μA
ILO
(3)
Output Leakage Current 10 10 10 10 μA
VOH Output Logic “1” Voltage IOH = –2mA 2.4 2.4 V
VOL Output Logic “0” Voltage IOL = 8mA 0.4 0.4 V
ICC1
(4,5)
Active Power Supply Current 60 75 mA
ICC2
(4,6)
Standby Current (R=W=RS=FL/RT=VIH)—55mA
NOTES:
1. Industrial temperature range product for the 25ns speed grade is available as a standard device. All other speed grades are available by special order.
2. Measurements with 0.4 VIN VCC.
3. R VIH, 0.4 VOUT VCC.
4. Tested with outputs open (IOUT = 0).
5. Tested at f = 20 MHz.
6. All Inputs = VCC - 0.2V or GND + 0.2V.
PLCC (J32-1, order code: J)
TOP VIEW
Symbol Rating Min. Typ. Max. Unit
VCC Supply Voltage 3.0 3.3 3.6 V
GND Supply Voltage 0 0 0 V
VIH
(1)
Input High Voltage 2.0 VCC+0.5 V
VIL
(2)
Input Low Voltage 0.8 V
TA Operating Temperature Commercial 0 70 °C
TA Operating Temperature Industrial –40 85 °C
Symbol Rating Com'l & Ind'l Unit
VTERM Terminal Voltage –0.5 to +7.0 V
with Respect to GND
TSTG Storage Temperature –55 to +125 °C
I
OUT DC Output Current –50 to +50 mA
NOTES:
1. For RT/RS/XI input, VIH = 2.6V (commercial).
For RT/RS/XI input, VIH = 2.8V (military).
2. 1.5V undershoots are allowed for 10ns once per cycle.
D
2
5
D
1
6
D
0
7
XI
8
FF
9
Q
0
10
Q
1
11
NC 12
Q
2
13
D
6
D
7
NC
FL/RT
RS
EF
XO/HF
Q
7
Q
6
29
28
27
26
25
24
23
22
21
4
3 2
1
32 31 30
14 15 16 17 18 19 20
Q
3
Q
8
GND
NC
R
Q
4
Q
5
D
3
D
8
W
NC
V
CC
D
4
D
5
INDEX
3033 drw 02b
Symbol Parameter
(1)
Condition Max. Unit
CIN Input Capacitance VIN = 0V 8 pF
C
OUT Output Capacitance VOUT = 0V 8 pF
RECOMMENDED DC OPERATING
CONDITIONS
ABSOLUTE MAXIMUM RATINGS
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.3V, TA = –40°C to +85°C)
NOTE:
1. Characterized values, not currently tested.
CAPACITANCE
(TA = +25°C, f = 1.0 MHz)
3
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V01/72V02/72V03/72V04/72V05/72V06 3.3V ASYNCHRONOUS FIFO
512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9, 8,192 x 9 and 16,384 x 9
AC ELECTRICAL CHARACTERISTICS
(1)
(Commercial: VCC = 3.3V ± 0.3V, TA = 0°C to +70°C; Industrial: VCC = 3.3V ± 0.3V, TA = –40°C to +85°C)
Commercial Com'l and Ind'l
(2)
Commercial
IDT72V01L15 IDT72V01L25 IDT72V01L35
IDT72V02L15 IDT72V02L25 IDT72V02L35
IDT72V03L15 IDT72V03L25 IDT72V03L35
IDT72V04L15 IDT72V04L25 IDT72V04L35
IDT72V05L15 IDT72V05L25 IDT72V05L35
IDT72V06L15 IDT72V06L25 IDT72V06L35
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
fS Shift Frequency 40 28.5 22.2 M Hz
tRC Read Cycle Time 25 35 45 ns
tA Access Time 15 25 35 ns
tRR Read Recovery Time 10 10 10 ns
tRPW Read Pulse Width
(3)
15 25 35 ns
tRLZ Read Pulse Low to Data Bus at Low Z
(4)
3—3—3 ns
tWLZ Write Pulse High to Data Bus at Low Z
(4,5)
5—5—5 ns
tDV Data Valid from Read Pulse High 5 5 5 ns
tRHZ Read Pulse High to Data Bus at High Z
(4)
15— 18— 20ns
tWC Write Cycle Time 25 35 45 ns
tWPW Write Pulse Width
(3)
15 25 35 ns
tWR Write Recovery Time 10 10 10 ns
tDS Data Setup Time 11 15 18 ns
tDH Data Hold Time 0 0 0 ns
tRSC Reset Cycle Time 25 35 45 ns
tRS Reset Pulse Width
(3)
15 25 35 ns
tRSS Reset Setup Time
(4)
15 25 35 ns
tRSR Reset Recovery Time 10 10 10 ns
tRTC Retransmit Cycle Time 25 35 45 ns
tRT Retransmit Pulse Width
(3)
15 25 35 ns
tRTS Retransmit Setup Time
(4)
15 25 35 ns
tRTR Retransmit Recovery Time 10 10 10 ns
tEFL Reset to Empty Flag Low 25 35 45 ns
tHFH,FFH Reset to Half-Full and Full Flag High 25 35 45 ns
tRTF Retransmit Low to Flags Valid 25 35 45 ns
tREF Read Low to Empty Flag Low 15 25 30 ns
tRFF Read High to Full Flag High 15 25 30 ns
tRPE Read Pulse Width after EF High 15 25 35 ns
tWEF Write High to Empty Flag High 15 25 30 ns
tWFF Write Low to Full Flag Low 15 25 30 ns
tWHF Write Low to Half-Full Flag Low 25 35 45 ns
tRHF Read High to Half-Full Flag High 25 35 45 ns
tWPF Write Pulse Width after FF High 15 25 35 ns
tXOL Read/Write to XO Low 15— 25— 35ns
tXOH Read/Write to XO High 15 25 35 ns
tXI XI Pulse Width
(3)
15 25 35 ns
tXIR XI Recovery Time 10 10 10 ns
t
XIS XI Setup Time 10 10 10 ns
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Industrial temperature range product for the 25ns speed grade is available as a standard device.
All other speed grades are available by special order.
3. Pulse widths less than minimum value are not allowed.
4. Values guaranteed by design, not currently tested.
5. Only applies to read data flow-through mode.
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 1
Figure 1. Output Load
* Includes scope and jig capacitances.
or equivalent circuit
3033 drw 03
30pF*
330Ω
3.3V
D.U.T.
510Ω

72V01L25JGI8

Mfr. #:
Manufacturer:
IDT
Description:
FIFO FIFO
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union