10
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
03/03/09
IS42S32400D
Current State
CSCS
CSCS
CS
RAS RAS
RAS RAS
RAS
CASCAS
CASCAS
CAS
WE WE
WE WE
WE Address Command Action
Read with auto H × × × × DESL Continue burst to end, Precharge
Precharging
L H H H x NOP Continue burst to end, Precharge
L H H L × BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL
(11)
L H L L BA, CA, A10 WRIT/ WRITA ILLEGAL
(11)
L L H H BA, RA ACT ILLEGAL
(3)
L L H L BA, A10 PRE/PALL ILLEGAL
(11)
L L L H × REF/SELF ILLEGAL
L L L L OC, BA MRS ILLEGAL
Write with Auto H × × × × DESL Continue burst to end, Write
Precharge recovering with auto precharge
L H H H × NOP Continue burst to end, Write
recovering with auto precharge
L H H L × BST ILLEGAL
L H L H BA, CA, A10 READ/READA ILLEGAL
(11)
L H L L BA, CA, A10 WRIT/ WRITA ILLEGAL
(11)
L L H H BA, RA ACT ILLEGAL
(3,11)
L L H L BA, A10 PRE/PALL ILLEGAL
(3,11)
L L L H × REF/SELF ILLEGAL
L L L L OC, BA MRS ILLEGAL
Precharging H × × × × DESL Nop, Enter idle after tRP
L H H H × NOP Nop, Enter idle after tRP
L H H L × BST Nop, Enter idle after tRP
L H L H BA, CA, A10 READ/READA ILLEGAL
(3)
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
(3)
L L H H BA, RA ACT ILLEGAL
(3)
L L H L BA, A10 PRE/PALL Nop Enter idle after tRP
L L L H × REF/SELF ILLEGAL
L L L L OC, BA MRS ILLEGAL
Row Activating H × × × × DESL Nop, Enter bank active after tRCD
L H H H × NOP Nop, Enter bank active after tRCD
L H H L × BST Nop, Enter bank active after tRCD
L H L H BA, CA, A10 READ/READA ILLEGAL
(3)
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
(3)
L L H H BA, RA ACT ILLEGAL
(3,9)
L L H L BA, A10 PRE/PALL ILLEGAL
(3)
L L L H × REF/SELF ILLEGAL
L L L L OC, BA MRS ILLEGAL
FUNCTIONAL TRUTH TABLE Continued:
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
IS42S32400D
Integrated Silicon Solution, Inc. — www.issi.com
11
Rev. F
03/03/09
Current State
CSCS
CSCS
CS
RAS RAS
RAS RAS
RAS
CASCAS
CASCAS
CAS
WE WE
WE WE
WE Address Command Action
Write Recovering H × × × × DESL Nop, Enter row active after tDPL
L H H H × NOP Nop, Enter row active after tDPL
L H H L × BST Nop, Enter row active after tDPL
L H L H BA, CA, A10 READ/READA Begin read
(8)
L H L L BA, CA, A10 WRIT/ WRITA Begin new write
L L H H BA, RA ACT ILLEGAL
(3)
L L H L BA, A10 PRE/PALL ILLEGAL
(3)
L L L H × REF/SELF ILLEGAL
L L L L OC, BA MRS ILLEGAL
Write Recovering H × × × × DESL Nop, Enter precharge after tDPL
with Auto L H H H × NOP Nop, Enter precharge after tDPL
Precharge L H H L × BST Nop, Enter row active after tDPL
L H L H BA, CA, A10 READ/READA ILLEGAL
(3,8,11)
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
(3,11)
L L H H BA, RA ACT ILLEGAL
(3,11)
L L H L BA, A10 PRE/PALL ILLEGAL
(3,11)
L L L H × REF/SELF ILLEGAL
L L L L OC, BA MRS ILLEGAL
Refresh H × × × × DESL Nop, Enter idle after tRC
L H H × × NOP/BST Nop, Enter idle after tRC
L H L H BA, CA, A10 READ/READA ILLEGAL
L H L L BA, CA, A10 WRIT/WRITA ILLEGAL
L L H H BA, RA ACT ILLEGAL
L L H L BA, A10 PRE/PALL ILLEGAL
L L L H × REF/SELF ILLEGAL
L L L L OC, BA MRS ILLEGAL
Mode Register H × × × × DESL Nop, Enter idle after 2 clocks
Accessing L H H H × NOP Nop, Enter idle after 2 clocks
L H H L × BST ILLEGAL
L H L × BA, CA, A10 READ/WRITE ILLEGAL
L L × × BA, RA ACT/PRE/PALL ILLEGAL
REF/MRS
FUNCTIONAL TRUTH TABLE Continued:
Note: H=VIH, L=VIL x= VIH or VIL, V = Valid Data, BA= Bank Address, CA+Column Address, RA=Row Address, OC= Op-Code
Notes:
1. All entries assume that CKE is active (CKEn-1=CKEn=H).
2. If both banks are idle, and CKE is inactive (Low), the device will enter Power Down mode. All input buffers except CKE will
be disabled.
3. Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the
state of that bank.
4. If both banks are idle, and CKE is inactive (Low), the device will enter Self-Refresh mode. All input buffers except CKE will
be disabled.
5. Illegal if tRCD is not satisfied.
6. Illegal if tRAS is not satisfied.
7. Must satisfy burst interrupt condition.
8. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
9. Must mask preceding data which don’t satisfy tDPL.
10. Illegal if tRRD is not satisfied.
11. Illegal for single bank, but legal for other banks.
12
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
03/03/09
IS42S32400D
CKE RELATED COMMAND TRUTH TABLE
(1)
CKE
Current State Operation n-1 n CS RAS CAS WE Address
Self-Refresh (S.R.) INVALID, CLK (n - 1) would exit S.R. H XXXXXX
Self-Refresh Recovery
(2)
LHHXXXX
Self-Refresh Recovery
(2)
LHL HHXX
Illegal L H L H L X X
Illegal L H L L X X X
Maintain S.R. L L XXXXX
Self-Refresh Recovery Idle After t
RC
HHHXXXX
Idle After t
RC
HHL HHXX
Illegal H H L H L X X
Illegal H H L L X X X
Begin clock suspend next cycle
(5)
HLHXXXX
Begin clock suspend next cycle
(5)
HL L HHXX
Illegal H L L H L X X
Illegal H L L L X X X
Exit clock suspend next cycle
(2)
LHXXXXX
Maintain clock suspend L L XXXXX
Power-Down (P.D.) INVALID, CLK (n - 1) would exit P.D. H XXXXX
EXIT P.D. --> Idle
(2)
LHXXXXX
Maintain power down mode L L XXXXX
Both Banks Idle Refer to operations in Operative Command Table H H H X X X
Refer to operations in Operative Command Table H H L H X X
Refer to operations in Operative Command Table H H L L H X
Auto-Refresh H H L L L H X
Refer to operations in Operative Command Table H H LLLLOp - Code
Refer to operations in Operative Command Table H L H X X X
Refer to operations in Operative Command Table H L L H X X
Refer to operations in Operative Command Table H L L L H X
Self-Refresh
(3)
HLLLLHX
Refer to operations in Operative Command Table H LLLLLOp - Code
Power-Down
(3)
LXXXXXX
Any state Refer to operations in Operative Command Table H H XXXXX
other than Begin clock suspend next cycle
(4)
HLXXXXX
listed above Exit clock suspend next cycle L H XXXXX
Maintain clock suspend L L XXXXX
Notes:
1. H : High level, L : low level, X : High or low level (Don’t care).
2. CKE Low to High transition will re-enable CLK and other inputs asynchronously. A minimum
setup time must be satisfied
before any command other than EXIT.
3. Power down and Self refresh can be entered only from the both banks idle state.
4. Must be legal command as defined in Operative Command Table.
5. Illegal if t
XSR is not satisfied.

IS42S32400D-7T-TR

Mfr. #:
Manufacturer:
Description:
IC DRAM 128M PARALLEL 86TSOP II
Lifecycle:
New from this manufacturer.
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