16
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
03/03/09
IS42S32400D
AC ELECTRICAL CHARACTERISTICS
(1,2,3)
-6 -7
Symbol Parameter Min. Max. Min. Max. Units
t
CK3 Clock Cycle Time CAS Latency = 3 6 7 ns
tCK2 CAS Latency = 2 8 10 ns
tAC3 Access Time From CLK CAS Latency = 3 5.4 5.4 ns
tAC2 CAS Latency = 2 6.5 6.5 ns
tCHI CLK HIGH Level Width 2.5 2.5 ns
tCL CLK LOW Level Width 2.5 2.5 ns
tOH3 Output Data Hold Time CAS Latency = 3 2.7 2.7 ns
tOH2 CAS Latency = 2 2.7 3 ns
tLZ Output LOW Impedance Time 0 0 ns
tHZ Output HIGH Impedance Time 2.7 5.4 2.7 5.4 ns
tDS Input Data Setup Time
(2)
1.5 1.5 ns
tDH Input Data Hold Time
(2)
0.8 0.8 ns
tAS Address Setup Time
(2)
1.5 1.5 ns
tAH Address Hold Time
(2)
0.8 0.8 ns
tCKS CKE Setup Time
(2)
1.5 1.5 ns
tCKH CKE Hold Time
(2)
0.8 0.8 ns
tCS Command Setup Time (CS, RAS, CAS, WE, DQM)
(2)
1.5 1.5 ns
tCH Command Hold Time (CS, RAS, CAS, WE, DQM)
(2)
0.8 0.8 ns
tRC Command Period (REF to REF / ACT to ACT) 60 67.5 ns
tRAS Command Period (ACT to PRE) 42
100K
45
100K
ns
tRP Command Period (PRE to ACT) 18 20 ns
tRCD Active Command To Read / Write Command Delay Time 18 20 ns
tRRD Command Period (ACT [0] to ACT[1]) 12 14 ns
tDPL Input Data To Precharge 12 14 ns
Command Delay time
tDAL Input Data To Active / Refresh
30
34
—ns
Command Delay time (During Auto-Precharge)
tMRD Mode Register Program Time 12 15 ns
tDDE Power Down Exit Setup Time 6 7.5 ns
tXSR Self-Refresh Exit Time 70 70 ns
tT Transition Time 1 10 1 10 ns
tREF Refresh Cycle Time (4096) 64 64 ms
Notes:
1. The power-on sequence must be executed before starting memory operation.
2. Measured with t
T = 1 ns. If clock rising time is longer than 1ns, (tR /2 - 0.5) ns should be added to the parameter.
3.
The reference level is 1.4V when measuring input signal timing. Rise and fall times are measured between V
IH
(min.) and V
IL
(max).
IS42S32400D
Integrated Silicon Solution, Inc. — www.issi.com
17
Rev. F
03/03/09
OPERATING FREQUENCY / LATENCY RELATIONSHIPS
SYMBOL PARAMETER UNITS
Clock Cycle Time 6 7 8 10 ns
Operating Frequency 166 143 125 100 MHz
tCAC CAS Latency 3 3 2/3 2/3 cycle
tRCD Active Command To Read/Write Command Delay Time 3 3 3 2 cycle
tRAC RAS Latency (tRCD + tCAC) CAS Latency = 3 6 6 6 5 cycle
CAS Latency = 2 5 4
tRC Command Period (REF to REF / ACT to ACT) 10 10 8 7 cycle
tRAS Command Period (ACT to PRE) 7 7 6 5 cycle
tRP Command Period (PRE to ACT) 3 3 3 2 cycle
tRRD Command Period (ACT[0] to ACT [1]) 2 2 2 2 cycle
tCCD Column Command Delay Time 1 1 1 1 cycle
(READ, READA, WRIT, WRITA)
tDPL Input Data To Precharge Command Delay Time 2 2 2 2 cycle
tDAL Input Data To Active/Refresh Command Delay Time 5 5 4 4 cycle
(During Auto-Precharge)
tRBD Burst Stop Command To Output in HIGH-Z Delay Time CAS Latency = 3 3 3 3 3 cycle
(Read) CAS Latency = 2 2 2
tWBD Burst Stop Command To Input in Invalid Delay Time 0 0 0 0 cycle
(Write)
tRQL Precharge Command To Output in HIGH-Z Delay Time CAS Latency = 3 3 3 3 3 cycle
(Read) CAS Latency = 2 2 2
tWDL Precharge Command To Input in Invalid Delay Time 0 0 0 0 cycle
(Write)
tPQL
Last Output To Auto-Precharge Start Time (Read)
CAS Latency = 3 -2 –2 -2 -2 cycle
CAS Latency = 2 -1 -1
tQMD DQM To Output Delay Time (Read) 2 2 2 2 cycle
tDMD DQM To Input Delay Time (Write) 0 0 0 0 cycle
tMRD Mode Register Set To Command Delay Time 2 2 2 2 cycle
18
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
03/03/09
IS42S32400D
AC TEST CONDITIONS
Input Load Output Load
Output
Z
= 50Ω
50 pF
1.4V
50Ω
3.0V
1.4V
0V
CLK
INPUT
OUTPUT
t
CHI
t
CH
t
AC
t
OH
t
CS
t
CK
t
CL
3.0V
1.4V
1.4V 1.4V
0V
AC TEST CONDITIONS
Parameter Rating
AC Input Levels 0V to 3.0V
Input Rise and Fall Times 1 ns
Input Timing Reference Level 1.4V
Output Timing Measurement Reference Level 1.4V

IS42S32400D-7T-TR

Mfr. #:
Manufacturer:
Description:
IC DRAM 128M PARALLEL 86TSOP II
Lifecycle:
New from this manufacturer.
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