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IS42S32400D-7T-TR

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60
IS42S32400D
Integrated Silicon Solution, Inc. — www.issi.com
31
Rev. F
03/03/09
DON'T CARE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5
READ
READ
READ
READ
NOP NOP
DOUT n
DOUT b
DOUT m
DOUT x
BANK,
COL n
BANK,
COL b
CAS Latency - 2
BANK,
COL m
BANK,
COL x
DON'T CARE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6
READ
READ
READ
READ
NOP NOP NOP
D
OUT
n
D
OUT
b
D
OUT
m
D
OUT
x
BANK,
COL n
BANK,
COL b
CAS Latency - 3
BANK,
COL m
BANK,
COL x
RANDOM READ ACCESSES
32
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
03/03/09
IS42S32400D
DON'T CARE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6
READ
NOP NOP NOP NOP NOP
D
OUT
n
D
OUT
n+1
D
OUT
n+2
D
OUT
n+3
BANK a,
COL n
CAS Latency - 2
x = 1 cycle
BURST
TERMINATE
DON'T CARE
CLK
COMMAND
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
READ
NOP NOP NOP NOP NOP NOP
DOUT n
DOUT n+1
DOUT n+2
DOUT n+3
BANK,
COL n
CAS Latency - 3
x = 2 cycles
BURST
TERMINATE
READ BURST TERMINATION
IS42S32400D
Integrated Silicon Solution, Inc. — www.issi.com
33
Rev. F
03/03/09
ALTERNATING BANK READ ACCESSES
BANK 0 BANK 3 BANK 3 BANK 0
DON'T CARE
CLK
CKE
COMMAND
DQM0 - DQM3
A0-A9, A11
A10
BA0, BA1
DQ
t
CMS
t
CMH
t
AS
t
AH
t
AS
t
AH
t
AS
t
AH
t
RCD
- BANK 0
CAS Latency - BANK 0
tRCD
- BANK 0
t
RAS
- BANK 0
t
RC
- BANK 0
t
CH
t
CL
t
CK
t
CMS
t
CMH
t
CKS
t
CKH
ACTIVE
NOP READ NOP
ACTIVE
NOP READ NOP
ACTIVE
ROW
ROW
BANK 0
ROW ROW
t
RRD
t
RCD
- BANK 3
t
RP
- BANK 0
COLUMN m
(2)
ROW
COLUMN b
(2)
ROW
ENABLE AUTO PRECHARGE ENABLE AUTO PRECHARGE
T0 T1 T2 T3 T4 T5 T6 T7 T8
t
AC
t
OH
t
OH
t
OH
t
OH
t
OH
DOUT m DOUT m+
1
DOUT m+
2
DOUT m+
3
DOUT b
t
AC
t
AC
t
AC
t
AC
t
AC
t
LZ
CAS Latency - BANK 3
Notes:
1) CAS latency = 2, Burst Length = 4
2) X32: A8, A9, A11 = "Don't Care"
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P51P52-P54P55-P57P58-P60

IS42S32400D-7T-TR

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Description:
IC DRAM 128M PARALLEL 86TSOP II
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