IS42S32400D
Integrated Silicon Solution, Inc. — www.issi.com
49
Rev. F
03/03/09
DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
NOP NOP NOP NOP NOP NOP
D
IN
a
D
IN
a+1
D
OUT
b
D
OUT
b+1
BANK n,
COL a
BANK m,
COL b
CAS Latency - 3 (BANK m)
t
RP - BANK n
t
RP - BANK m
WRITE - AP
BANK n
READ - AP
BANK m
Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge
Page Active READ with Burst of 4 Precharge
Internal States
t
DPL
- BANK n
DON'T CARE
CLK
COMMAND
BANK n
BANK m
ADDRESS
DQ
T0 T1 T2 T3 T4 T5 T6 T7
NOP NOP NOP NOP NOP NOP
BANK n,
COL a
BANK m,
COL b
t
RP - BANK n
t
DPL - BANK m
WRITE - AP
BANK n
WRITE - AP
BANK m
Page Active WRITE with Burst of 4 Interrupt Burst, Write-Back Precharge
Page Active WRITE with Burst of 4 Write-Back
Internal States
t
DPL
- BANK n
D
IN
a
D
IN
a+1 D
IN
a+2
D
IN
b
D
IN
b+1 D
IN
b+2 D
IN
b+3
WRITE with Auto Precharge
3. Interrupted by a READ (with or without auto precharge):
A READ to bank m will interrupt a WRITE on bank n when
registered, with the data-out appearing
(CAS latency)
later.
The PRECHARGE to bank n will begin after t
DPL is met,
where tDPL begins when the READ to bank m is registered.
The last valid
WRITE
to bank n will be data-in registered one
clock prior to the READ to bank m.
4. Interrupted by a WRITE (with or without auto precharge):
A
WRITE
to bank m will interrupt a
WRITE
on bank n when
registered. The PRECHARGE to bank n will begin after
tDPL is met, where tDPL begins when the WRITE to bank m
is registered. The last valid data WRITE to bank n will be
data registered one clock prior to a WRITE to bank m.
WRITE With Auto Precharge interrupted by a READ
WRITE With Auto Precharge interrupted by a WRITE
50
Integrated Silicon Solution, Inc. — www.issi.com
Rev. F
03/03/09
IS42S32400D
SINGLE READ WITH AUTO PRECHARGE
DON'T CARE
UNDEFINED
CLK
CKE
COMMAND
DQM0 - DQM3
A0-A9, A11
A10
BA0, BA1
DQ
t
CMS
t
CMH
ACTIVE NOP NOP NOP READ NOP NOP ACTIVE NOP
t
AS
t
AH
t
AS
t
AH
t
AS
t
AH
ROW
ROW
BANK
COLUMN m
(2)
t
CH
t
CL
t
CK
t
CMS
t
CMH
t
CKS
t
CKH
BANK
t
RCD
t
RAS
t
RC
CAS Latency
t
AC
t
HZ
t
OH
D
OUT
m
T0 T1 T2 T3 T4 T5 T6 T7 T8
t
RP
ENABLE AUTO PRECHARGE
ROW
ROW
BANK
Notes:
1) CAS latency = 2, Burst Length = 1
2) X32: A8, A9, A11 = "Don't Care"
IS42S32400D
Integrated Silicon Solution, Inc. — www.issi.com
51
Rev. F
03/03/09
READ WITH AUTO PRECHARGE
DON'T CARE
UNDEFINED
CLK
CKE
COMMAND
DQM0 - DQM3
A0-A9, A11
A10
BA0, BA1
DQ
t
CMS
t
CMH
ACTIVE NOP READ NOP NOP NOP NOP NOP ACTIVE
t
AS
t
AH
t
AS
t
AH
t
AS
t
AH
ROW
ROW
BANK
COLUMN m
(2)
t
CH
t
CL
t
CK
t
CMS
t
CMH
t
CKS
t
CKH
BANK
t
RCD
t
RAS
t
RC
CAS Latency
t
AC
t
AC
t
AC
t
AC
tOH
t
HZ
tOH
D
OUT
m
tOH
D
OUT
m+1
tOH
D
OUT
m+2 D
OUT
m+3
T0 T1 T2 T3 T4 T5 T6 T7 T8
t
RP
ENABLE AUTO PRECHARGE
ROW
ROW
BANK
t
LZ
Notes:
1) CAS latency = 2, Burst Length = 4
2) X32: A8, A9, A11 = "Don't Care"

IS42S32400D-7T-TR

Mfr. #:
Manufacturer:
Description:
IC DRAM 128M PARALLEL 86TSOP II
Lifecycle:
New from this manufacturer.
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