1
CMOS DUAL ASYNCHRONOUS FIFO
DUAL 256 x 9, DUAL 512 x 9,
DUAL 1,024 x 9, DUAL 2,048 x 9,
DUAL 4,096 x 9, DUAL 8,192 x 9
IDT7280
IDT7281
IDT7282
IDT7283
IDT7284
IDT7285
JUNE 2012
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
©2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-3208/9
FEATURES:
The IDT7280 is equivalent to two IDT7200 256 x 9 FIFOs
The IDT7281 is equivalent to two IDT7201 512 x 9 FIFOs
The IDT7282 is equivalent to two IDT7202 1,024 x 9 FIFOs
The IDT7283 is equivalent to two IDT7203 2,048 x 9 FIFOs
The IDT7284 is equivalent to two IDT7204 4,096 x 9 FIFOs
The IDT7285 is equivalent to two IDT7205 8,192 x 9 FIFOs
Low power consumption
— Active: 685 mW (max.)
— Power-down: 83 mW (max.)
Ultra high speed—12 ns access time
Asynchronous and simultaneous read and write
Offers optimal combination of data capacity, small foot print
and functional flexibility
Ideal for bi-directional, width expansion, depth expansion,
bus-matching, and data sorting applications
Status Flags: Empty, Half-Full, Full
Auto-retransmit capability
High-performance CMOS technology
Space-saving TSSOP
Industrial temperature range (–40
°°
°°
°
C to +85
°°
°°
°
C) is available
DESCRIPTION:
The IDT7280/7281/7282/7283/7284/7285 are dual-FIFO memories that
load and empty data on a first-in/first-out basis. These devices are functional
and compatible to two IDT7200/7201/7202/7203/7204/7205 FIFOs in a single
package with all associated control, data, and flag lines assigned to separate
pins. The devices use Full and Empty flags to prevent data overflow and
underflow and expansion logic to allow for unlimited expansion capability in both
word size and depth.
The reads and writes are internally sequential through the use of ring pointers,
with no address information required to load and unload data. Data is toggled
in and out of the devices through the use of the Write (W) and Read (R) pins.
The devices utilize a 9-bit wide data array to allow for control and parity bits
at the user’s option. This feature is especially useful in data communications
applications where it is necessary to use a parity bit for transmission/reception
error checking. It also features a Retransmit (RT) capability that allows for reset
of the read pointer to its initial position when RT is pulsed LOW to allow for
retransmission from the beginning of data. A Half-Full Flag is available in the
single device mode and width expansion modes.
These FIFOs are fabricated using high-speed CMOS technology. They are
designed for those applications requiring asynchronous and simultaneous
read/writes in multiprocessing and rate buffer applications.
FUNCTIONAL BLOCK DIAGRAM
WA
WRITE
CONTROL
READ
CONTROL
RA
FLAG
LOGIC
EXPANSION
LOGIC
XIA
WRITE
POINTER
READ
POINTER
DATA INPUTS
RESET
LOGIC
THREE-
STATE
BUFFERS
DATA
OUTPUTS
RSA
FLA/RTA
XOA/HFA
FFA EFA
WB
WRITE
CONTROL
READ
CONTROL
RB
FLAG
LOGIC
EXPANSION
LOGIC
XIB
WRITE
POINTER
RAM
ARRAY B
256 x 9
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
READ
POINTER
DATA INPUTS
RESET
LOGIC
THREE-
STATE
BUFFERS
DATA
OUTPUTS
RSB
FLB/RTB
3208 drw 01
XOB/HFB
FFB EFB
(DA
0
-DA
8
)
(DB
0
-DB
8
)
(QB
0
-QB
8
)
(QA
0
-QA
8
)
RAM
ARRAY A
256 x 9
512 x 9
1,024 x 9
2,048 x 9
4,096 x 9
8,192 x 9
2
COMMERCIAL TEMPERATURE RANGE
IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO
DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
JUNE 29, 2012
PIN CONFIGURATION ABSOLUTE MAXIMUM RATINGS
Symbol Rating Com'l & Ind'l Unit
V
TERM Terminal Voltage with –0.5 to +7.0 V
Respect to GND
TSTG Storage Temperature –55 to +125 °C
I
OUT DC Output Current –50 to +50 mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 5ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
Output Load See Figure 1
CAPACITANCE (TA = +25
o
C, f = 1.0 MHz)
Symbol Parameter Condition Max. Unit
CIN Input Capacitance VIN = 0V 8 pF
C
OUT Output Capacitance VOUT = 0V 8 pF
NOTE:
1. Characterized values, not currently tested.
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 4.5 5.0 5.5 V
GND Supply Voltage 0 0 0 V
VIH
(1)
Input High Voltage 2.0 V
VIL
(2)
Input Low Voltage 0.8 V
TA Operating Temperature 0 70 °C
Commercial
TA Operating Temperature 40 85 °C
Industrial
NOTES:
1. For RT/RS/XI input, VIH = 2.6V (commercial).
2. 1.5V undershoots are allowed for 10ns once per cycle.
RECOMMENDED DC OPERATING
CONDITIONS
TSSOP (SO56-2, order code: PA)
TOP VIEW
FFA
QA
0
QA1
QA2
QA3
QA8
GND
RA
QA
4
QA5
QA6
QA7
XOA/HFA
EFA
FFB
QB
0
QB1
QB2
QB3
QB8
GND
RB
QB
4
QB5
QB6
QB7
XOB/HFB
EFB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
XIA
DA
0
DA1
DA2
DA3
DA8
WA
V
CC
DA4
DA5
DA6
DA7
FLA/RTA
RSA
XIB
DB
0
DB1
DB2
DB3
DB8
WB
V
CC
DB4
DB5
DB6
DB7
FLB/RTB
RSB
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
3208 drw 02
3208 drw 03
30pF*
1.1K
5V
TO
OUTPUT
PIN
680Ω
or equivalent circuit
IDT7280L IDT7283L
IDT7281L IDT7284L
IDT7282L IDT7285lL
Commercial & Industrial
(1)
Commercial & Industrial
(1)
tA = 12, 15 ns tA = 12, 15 ns
Symbol Parameter Min. Max. Min. Max. Unit
I
LI
(2)
Input Leakage Current (Any Input) 1 1 1 μA
ILO
(3)
Output Leakage Current 10 10 10 10 μA
V
OH Output Logic “1” Voltage IOH = –2mA 2.4 2.4 V
VOL Output Logic “0” Voltage IOL = 8mA 0.4 0.4 V
ICC1
(4,5)
Active Power Supply Current (both FIFOs) 125
(6)
—150mA
I
CC2
(4,7)
Standby Current (R=W=RS=FL/RT=VIH)—1515mA
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)
NOTES:
1.
Industrial temperature range product for the 15ns speed grade is available as a standard
device.
2. Measurements with 0.4 VIN VCC.
3. R VIH, 0.4 VOUT VCC.
4. Tested with outputs open (IOUT = 0).
5. Tested at f = 20 MHz.
6. Typical ICC1 = 2*[15 + 2*fS + 0.02*CL*fS] (in mA) with VCC = 5V, TA = 25
o
C, fS = WCLK
frequency = RCLK frequency (in MHz, using TTL levels), data switching at fS/2,
CL = capacitive load (in pF).
7. All Inputs = VCC - 0.2V or GND + 0.2V.
Figure 1. Output Load
* Includes scope and jig capacitances.
3
COMMERCIAL TEMPERATURE RANGE
IDT7280/7281/7282/7283/7284/7285 5V ASYNCHRONOUS FIFO
DUAL 256 x 9, 512 x 9, 1,024 x 9, 2,048 x 9, 4,096 x 9 and 8,192 x 9
JUNE 29, 2012
Commercial Commercial & Industrial
(2)
IDT7280L12 IDT7280L15
IDT7281L12 IDT7281L15
IDT7282L12 IDT7282L15
IDT7283L12 IDT7283L15
IDT7284L12 IDT7284L15
IDT7285L12 IDT7285L15
Symbol Parameter Min. Max. Min. Max. Unit
tS Shift Frequency 50 40 M H z
tRC Read Cycle Time 20 25 ns
tA Access Time 12 15 ns
tRR Read Recovery Time 8 10 ns
tRPW Read Pulse Width
(3)
12 15 ns
tRLZ Read Pulse Low to Data Bus at Low Z
(4)
3—3ns
tWLZ Write Pulse High to Data Bus at Low Z
(4,5)
5—5ns
tDV Data Valid from Read Pulse High 5 5 ns
tRHZ Read Pulse High to Data Bus at High Z
(4)
—1215ns
tWC Write Cycle Time 20 25 ns
tWPW Write Pulse Width
(3)
12 15 ns
tWR Write Recovery Time 8 10 ns
tDS Data Set-up Time 9 11 ns
tDH Data Hold Time 0 0 ns
tRSC Reset Cycle Time 20 25 ns
tRS Reset Pulse Width
(3)
12 15 ns
tRSS Reset Set-up Time
(4)
12 15 ns
tRSR Reset Recovery Time 8 10 ns
tRTC Retransmit Cycle Time 20 25 ns
tRT Retransmit Pulse Width
(3)
12 15 ns
tRTS Retransmit Set-up Time
(4)
12 15 ns
tRTR Retransmit Recovery Time 8 10 ns
tEFL Reset to Empty Flag Low 12 25 ns
tHFH,FFH Reset to Half-Full and Full Flag High 17 25 ns
tRTF Retransmit Low to Flags Valid 20 25 ns
tREF Read Low to Empty Flag Low 12 15 ns
tRFF Read High to Full Flag High 14 15 ns
tRPE Read Pulse Width after EF High 12 15 ns
tWEF Write High to Empty Flag High 12 15 ns
tWFF Write Low to Full Flag Low 14 15 ns
tWHF Write Low to Half-Full Flag Low 17 25 ns
tRHF Read High to Half-Full Flag High 17 25 ns
tWPF Write Pulse Width after FF High 12 15 ns
tXOL Read/Write to XO Low 12 15 ns
tXOH Read/Write to XO High 12 15 ns
tXI XI Pulse Width
(3)
12 15 ns
tXIR XI Recovery Time 8 10 ns
t
XIS XI Set-up Time 8 10 ns
NOTES:
1. Timings referenced as in AC Test Conditions.
2.
Industrial temperature range product for the 15ns speed grade is available as a standard device.
3. Pulse widths less than minimum value are not allowed.
4. Values guaranteed by design, not currently tested.
5. Only applies to read data flow-through mode.
AC ELECTRICAL CHARACTERISTICS
(1)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C)

7285L15PAGI

Mfr. #:
Manufacturer:
IDT
Description:
FIFO FIFO
Lifecycle:
New from this manufacturer.
Delivery:
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