OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

LTC2925IUF#PBF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26
LTC2925
13
2925fd
For more information www.linear.com/LTC2925
Status Output
The STATUS pin provides an indication that the supplies are
finished ramping up. This pin is an open-drain output that
pulls low until the GATE has been fully charged. Since the
GATE pin drives the gate of the external FET, or the RAMP
pin directly when no FET is used, the supplies are com
-
pletely ramped up when the GATE pin is fully charged. The
STATUS pin will go low again when the GATE pin is pulled
low, either because of a short-circuit fault, a power good
timeout fault, or because the ON pin has been pulled low.
Fault Output
The FAULT pin is an open-drain output that pulls low
when the electronic circuit breaker is activated due to a
short-circuit or power good timeout fault. FAULT is reset
by pulling ON below 0.4V. The supplies will not be allowed
to ramp up again until the SCTMR, PGTMR and SDTMR
pins are below about 100mV, and the ON pin is pulled
above 1.23V.
Retry on Fault
The LTC2925 continuously attempts to ramp up the
outputs after a fault if the FAULT pin is tied to the ON pin
(Figure 9). If a short-circuit fault occurs in this configu
-
ration, the SCTMR pin ramps up the C
SCTMR
capacitor
with 50µA until it reaches 1.23V. Then, GATE is pulled
low turning off the shorted FET. At the same time, the
FAULT pin’s open-drain output pulls ON low. The C
SCTMR
capacitor is pulled down with 2µA until it reaches about
100mV. After the C
SCTMR
capacitor reaches 100mV, the
shutdown timer begins and upon completing a shutdown
timer cycle, the supplies start ramping up again. If there
is no short-circuit this time, the supplies will come up
normally. Otherwise the retry cycle will repeat. If a longer
off time is required between retry attempts, the C
SDTMR
capacitor value can be increased, providing a greater delay
before the FET’s GATE ramps up on each cycle. Note that
tying FAULT to ON also causes the LTC2925 to retry on
Power Good Timeout faults. In this mode, verify that the
slave supplies’ current limits provide sufficient protection
under short-circuit conditions.
applicaTions inForMaTion
R
SENSE
Q1
0.1µF
C
PGTMR
V
CC
SENSEP SENSEN
V
IN
V
IN
R
ONB
V
IN
R
TB1
R
TB2
R
FA2
SLAVE2
MASTER
R
FB2
R
TA2
R
TB3
R
TA3
R
TA1
R
ONA
RAMPBUF
TRACK1
TRACK2
TRACK3
FB2
GATE
LTC2925
PGTMR
C
SDTMR
SDTMR
C
SCTMR
SCTMRGND
2925 F09
RAMP
R
FA3
SLAVE3
R
FB3
DC/DC
IN
FB OUT
DC/DC
IN
FB
RUN/SS
RUN/SS
OUT
FB3
V
IN
PGI
R
FA1
SLAVE1
R
FB1
SUPPLY
MONITOR
DC/DC
IN
FB
RUN/SS
OUT
FB1
FAULT
ON
10k
V
IN
STATUS
REMOTE
RST
SD3
SD2
SD1
C
GATE
10Ω
Figure 9. Retry on Fault
LTC2925
14
2925fd
For more information www.linear.com/LTC2925
3-Step Design Procedure
The following 3-step design procedure allows one to
choose the TRACK resistors, R
TAx
and R
TBx
, and the gate
capacitor, C
GATE
, that give any of the tracking or sequenc-
ing profiles shown in Figures 1 to 4. A basic four supply
application circuit is shown in Figure 10.
1.
Set the ramp rate of the master signal.
Solve for the value of C
GATE
, the capacitor on the GATE
pin, based on the desired ramp rate (V/s) of the master
supply, S
M
:
C
I
S
whereIA
GATE
GATE
M
GATE
=≈μ10 1
()
If the external FET has a gate capacitance comparable
to C
GATE
, then the external capacitor’s value should be
reduced to compensate for the FET’s gate capacitance.
If no external FET is used, tie the GATE and RAMP pins
together, connect SENSEN and SENSEP to V
CC
, and con-
nect SCTMR to GND.
2. So
lve for the pair of resistors that provide the desired
ramp rate of the slave supply, assuming no delay.
Choose a ramp rate for the slave supply, S
S
. If the slave
supply ramps up coincident with the master supply or
with a fixed voltage offset, then the ramp rate equals the
master supply’s ramp rate. Be sure to use a fast enough
ramp rate for the slave supply so that it will finish ramping
before the master supply has reached its final supply value.
If not, the slave supply will be held below the intended
regulation value by the master supply. Use the following
formulas to determine the resistor values for the desired
ramp rate, where R
FB
and R
FA
are the feedback resistors in
the slave supply and V
FB
is the feedback reference voltage
of the slave supply:
RR
S
S
TB FB
M
S
=
•(
)2
R
V
V
R
V
R
V
R
TA
TRACK
FB
FB
FB
FA
TRACK
TB
ʹ=
+ –
()
3
where V
TRACK
≈ 0.8V.
Note that large ratios of slave ramp rate to master ramp
rate, S
S
/S
M
, may result in negative values for R
TA
´. If a
sufficiently large delay is used in step 3, R
TA
will be posi-
tive, otherwise S
S
/S
M
must be reduced.
3. Choose R
TA
to obtain the desired delay.
If no delay is required, such as in coincident and ratiometric
tracking, then simply set R
TA
= R
TA
´. If a delay is desired,
as in offset tracking and supply sequencing, calculate R
TA
´´
to determine the value of R
TA
where t
D
is the desired delay.
R
VR
tS
TA
TRACK TB
DM
ʹʹ =
•
•
()
4
RRR
TA TA TA
=ʹ ʹʹ
|| ()5
the parallel combination of R
TA
´ and R
TA
´´.
As noted in step 2, small delays and large ratios of slave
ramp rate to master ramp rate (usually only seen in se
-
quencing) may result in solutions with negative values for
R
TA
. In such cases, either the delay must be increased or
the ratio of slave ramp rate to master ramp rate must be
reduced.
applicaTions inForMaTion
R
SENSE
Q1
0.1µF
10k
V
CC
SENSEP SENSEN
V
IN
V
IN
V
IN
R
ONB
138k
V
IN
R
TB1
R
TB2
R
FA2
SLAVE2
MASTER
R
FB2
R
TA2
R
TB3
R
TA3
R
TA1
R
ONA
100k
RAMPBUF
TRACK1
TRACK2
TRACK3
FB2
GATE
LTC2925
PGTMR
SDTMRSCTMRGND
2925 F10
RAMP
R
FA3
SLAVE3
R
FB3
DC/DC
IN
FB OUT
DC/DC
IN
FB
RUN/SS
RUN/SS
OUT
FB3
V
IN
PGI
R
FA1
SLAVE1
R
FB1
SUPPLY
MONITOR
DC/DC
IN
FB
RUN/SS
OUT
FB1
FAULT
ON
10k
V
IN
STATUS
REMOTE
RST
SD3
SD2
SD1
C
GATE
10Ω
Figure 10. Four Supply Application
LTC2925
15
2925fd
For more information www.linear.com/LTC2925
applicaTions inForMaTion
Coincident Tracking Example
A typical four supply application is shown in Figure 12.
The master signal is a 3.3V module. The slave 1 supply
is a 1.8V switching power supply, the slave 2 supply is a
2.5V switching power supply, and the slave 3 supply is
a 1.5V supply. All three slave supplies track coincidently
with the 3.3V supply that is controlled with an external FET.
The ramp rate of the supplies is 100V/s. The 3-step design
procedure detailed previously can be used to determine
component values. Only the slave 1 supply is considered
here as the procedure is the same for the other supplies.
1. Set the ramp rate of the master signal.
From Equation 1:
C
µA
Vs
µF
GATE
10
100
01
/
.
2. Solve for the pair of resistors that provide the desired
slave supply behavior, assuming no delay.
From Equation 2:
Rk
Vs
Vs
k
TB
==
16 5
100
100
16 5.•
/
/
.
From Equation 3:
R
V
V
k
V
k
V
k
k
TA
ʹ=
+
≈
08
1 235
16 5
1 235
35 7
08
16 5
13
.
.
.
.
.
–
.
.
3. Choose RTA to obtain the desired delay.
Since no delay is desired, R
TA
= R
TA
´.
MASTER
SLAVE2
SLAVE1
1V/DIV
1V/DIV
SLAVE3
10ms/DIV 10ms/DIV
2925 F11
Figure 11. Coincident Tracking from Figure 12
0.015Ω
Q1
Si4412ADY
0.1µF
C
PGTMR
0.82µF
10k
V
CC
SENSEP SENSEN
3.3V
V
IN
3.3V
R
ONB
138k
3.3V V
IN
R
TB1
16.5k
R
TB2
88.7k
R
FA2
41.2k
2.5V
SLAVE2
MASTER
R
FB2
88.7k
R
TA2
41.2k
R
TB3
86.6k
R
TA3
100k
R
TA1
13k
R
ONA
100k
RAMPBUF
TRACK1
TRACK2
TRACK3
FB2
GATE
LTC2925
PGTMR
C
SDTMR
0.082µF
SDTMR
C
SCTMR
0.47µF
SCTMR
GND
2925 F12
RAMP
R
FA3
100k
1.5V
SLAVE3
R
FB3
86.6k
DC/DC
IN
FB = 0.8V OUT
DC/DC
IN
FB = 0.8V
RUN/SS
RUN/SS
OUT
FB3
3.3V
PGI
R
FA1
35.7k
1.8V
SLAVE1
R
FB1
16.5k
SUPPLY
MONITOR
DC/DC
IN
FB = 1.235V
RUN/SS
OUT
FB1
FAULT
ON
10k
V
IN
STATUS
REMOTE
RST
SD3
SD2
SD1
C
GATE
0.1µF
10Ω
In this example, all supplies remain low while the ON pin
is held below 1.23V. When the ON pin rises above 1.23V,
10µA pulls up CGATE and the gate of the FET at 100V/s.
As the gate of the FET rises, the source follows and pulls
up the output to 3.3V at 100V/s. This output serves as
the master signal and is buffered from the RAMP pin
to the RAMPBUF pin. As this output and the RAMPBUF
pin rise, the current from the TRACKx pins is reduced.
Consequently, the voltages at the slave supplies’ outputs
increase, and the slave supplies track the master supply.
When the ON pin is again pulled below 1.23V, 10µA will
pull down C
GATE
and the gate of the FET at 100V/s. If the
loads on the outputs are sufficient, all outputs will track
down coincidently at 100V/s.
Figure 12. Coincident Tracking Example
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P26

LTC2925IUF#PBF

Mfr. #:
Buy LTC2925IUF#PBF
Manufacturer:
Analog Devices Inc.
Description:
Power Management Specialized - PMIC Pwr Supply Sequence/Tracking Controller
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet