Table 10: I
DD
Specifications and Conditions – 1GB (Die Revision H)
Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-
ponent data sheet
Parameter/Condition Symbol
-80E
-800 -667 Units
Operating one bank active-precharge current:
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address
bus inputs are switching; Data bus inputs are switching
I
DD0
585 540 mA
Operating one bank active-read-precharge current: I
OUT
= 0mA; BL = 4, CL = CL
(I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RAS =
t
RAS MIN (I
DD
),
t
RCD =
t
RCD (I
DD
);
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data pattern is same as I
DD4W
I
DD1
675 630 mA
Precharge power-down current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is LOW;
Other control and address bus inputs are stable; Data bus inputs are floating
I
DD2P
63 63 mA
Precharge quiet standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is
HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs
are floating
I
DD2Q
216 216 mA
Precharge standby current: All device banks idle;
t
CK =
t
CK (I
DD
); CKE is HIGH, S#
is HIGH; Other control and address bus inputs are switching; Data bus inputs are
switching
I
DD2N
252 216 mA
Active power-down current: All device banks open;
t
CK =
t
CK
(I
DD
); CKE is LOW; Other control and address bus inputs are stable;
Data bus inputs are floating
Fast PDN exit
MR[12] = 0
I
DD3P
180 135 mA
Slow PDN exit
MR[12] = 1
90 90 mA
Active standby current: All device banks open;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX
(I
DD
),
t
RP =
t
RP (I
DD
); CKE is HIGH, S# is HIGH between valid commands; Other control
and address bus inputs are switching; Data bus inputs are switching
I
DD3N
297 270 mA
Operating burst write current: All device banks open; Continuous burst writes;
BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP (I
DD
);
CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;
Data bus inputs are switching
I
DD4W
1125 1035 mA
Operating burst read current: All device banks open; Continuous burst reads; I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL = 0;
t
CK =
t
CK (I
DD
),
t
RAS =
t
RAS MAX (I
DD
),
t
RP =
t
RP
(I
DD
); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are
switching; Data bus inputs are switching
I
DD4R
1080 990 mA
Burst refresh current:
t
CK =
t
CK (I
DD
); REFRESH command at every
t
RFC (I
DD
) inter-
val; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus
inputs are switching; Data bus inputs are switching
I
DD5
1305 1260 mA
Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus
inputs are floating; Data bus inputs are floating
I
DD6
63 63 mA
Operating bank interleave read current: All device banks interleaving reads;
I
OUT
= 0mA; BL = 4, CL = CL (I
DD
), AL =
t
RCD (I
DD
) - 1 ×
t
CK (I
DD
);
t
CK =
t
CK (I
DD
),
t
RC =
t
RC (I
DD
),
t
RRD =
t
RRD (I
DD
),
t
RCD =
t
RCD (I
DD
); CKE is HIGH, S# is HIGH between valid
commands; Address bus inputs are stable during deselects; Data bus inputs are
switching
I
DD7
1890 1665 mA
512MB, 1GB (x72, ECC, SR) 244-Pin DDR2 SDRAM Mini-RDIMM
I
DD
Specifications
PDF: 09005aef83f993e9
htf9c64_128x72pkz.pdf – Rev. C 4/14 EN
11
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