1
JUNE 2012
CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
IDT7200L
IDT7201LA
IDT7202LA
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
COMMERCIAL, INDUSTRIAL AND MILITARY TEMPERATURE RANGES
©2012 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-2679/14
FEATURES:
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• First-In/First-Out dual-port memory
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• 256 x 9 organization (IDT7200)
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• 512 x 9 organization (IDT7201)
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• 1,024 x 9 organization (IDT7202)
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• Low power consumption
— Active: 440mW (max.)
—Power-down: 28mW (max.)
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• Ultra high speed—12ns access time
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• Asynchronous and simultaneous read and write
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• Fully expandable by both word depth and/or bit width
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• 720x family is pin and functionally compatible from 256 x 9 to 64k x 9
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• Status Flags: Empty, Half-Full, Full
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• Auto-retransmit capability
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• High-performance CEMOS™ technology
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• Military product compliant to MIL-STD-883, Class B
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• Standard Military Drawing #5962-87531, 5962-89666, 5962-89863
and 5962-89536 are listed on this function
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• Dual versions available in the TSSOP package. For more informa-
tion, see IDT7280/7281/7282 data sheet
IDT7280 = 2 x IDT7200
IDT7281 = 2 x IDT7201
IDT7282 = 2 x IDT7202
DESCRIPTION:
The IDT7200/7201/7202 are dual-port memories that load and empty data
on a first-in/first-out basis. The devices use Full and Empty flags to prevent data
overflow and underflow and expansion logic to allow for unlimited expansion
capability in both word size and depth.
The reads and writes are internally sequential through the use of ring
pointers, with no address information required to load and unload data. Data
is toggled in and out of the devices through the use of the Write (W) and Read
(R) pins.
The devices utilize a 9-bit wide data array to allow for control and parity bits
at the user’s option. This feature is especially useful in data communications
applications where it is necessary to use a parity bit for transmission/reception
error checking. It also features a Retransmit (RT) capability that allows for reset
of the read pointer to its initial position when RT is pulsed LOW to allow for
retransmission from the beginning of data. A Half-Full Flag is available in the
single device mode and width expansion modes.
These FIFOs are fabricated using high-speed CMOS technology. They
are designed for those applications requiring asynchronous and simultaneous
read/writes in multiprocessing and rate buffer applications. Military grade
product is manufactured in compliance with MIL-STD-883, Class B.
FUNCTIONAL BLOCK DIAGRAM
W
WRITE
CONTROL
READ
CONTROL
R
FLAG
LOGIC
EXPANSION
LOGIC
XI
WRITE
POINTER
RAM
ARRAY
256 x 9
512 x 9
1,024 x 9
READ
POINTER
DATA INPUTS
RESET
LOGIC
THREE-
STATE
BUFFERS
DATA OUTPUTS
EF
FF
XO/HF
RS
FL/RT
(D
0
-D
8
)
2679 drw 01
(Q
0
-Q
8
)
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• Industrial temperature range (–40
o
C to +85
o
C) is available
(plastic packages only)
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Green parts available, see ordering information
