4
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
Commercial Com'l & Ind'l
(2)
Com'l & Mil. Com'l & Ind'l
(2)
IDT7200L12 IDT7200L15 IDT7200L20 IDT7200L25
IDT7201LA12 IDT7201LA15 IDT7201LA20 IDT7201LA25
IDT7202LA12 IDT7202LA15 IDT7202LA20 IDT7202LA25
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
t
S Shift Frequency 50 40 33.3 28.5 M H z
t
RC Read Cycle Time 20 25 30 35 ns
t
A Access Time 12 15 20 25 ns
t
RR Read Recovery Time 8 10 10 10 ns
t
RPW Read Pulse Width
(3)
12 15 20 25 ns
t
RLZ Read Pulse Low to Data Bus at Low Z
(4)
33—3—3—ns
t
WLZ Write Pulse High to Data Bus at Low Z
(4,5)
55—5—5—ns
t
DV Data Valid from Read Pulse High 5 5 5 5 ns
t
RHZ Read Pulse High to Data Bus at High Z
(4)
12 15 15 18 ns
t
WC Write Cycle Time 20 25 30 35 ns
t
WPW Write Pulse Width
(3)
12 15 20 25 ns
t
WR Write Recovery Time 8 10 10 10 ns
t
DS Data Set-up Time 9 11 12 15 ns
tDH Data Hold Time 0 0 0 0 ns
t
RSC Reset Cycle Time 20 25 30 35 ns
t
RS Reset Pulse Width
(3)
12 15 20 25 ns
t
RSS Reset Set-up Time
(4)
12 15 20 25 ns
t
RSR Reset Recovery Time 8 10 10 10 ns
t
RTC Retransmit Cycle Time 20 25 30 35 ns
tRT Retransmit Pulse Width
(3)
12 15 20 25 ns
t
RTS Retransmit Set-up Time
(4)
12 15 20 25 ns
t
RTR Retransmit Recovery Time 8 10 10 10 ns
tEFL Reset to Empty Flag Low 12 25 30 35 ns
t
HFH,FFH Reset to Half-Full and Full Flag High 17 25 30 35 ns
t
RTF Retransmit Low to Flags Valid 20 25 30 35 ns
tREF Read Low to Empty Flag Low 12 15 20 25 ns
t
RFF Read High to Full Flag High 14 15 20 25 ns
t
RPE Read Pulse Width after EF High 12 15 20 25 ns
tWEF Write High to Empty Flag High 12 15 20 25 ns
t
WFF Write Low to Full Flag Low 14 15 20 25 ns
t
WHF Write Low to Half-Full Flag Low 17 25 30 35 ns
tRHF Read High to Half-Full Flag High 17 25 30 35 ns
t
WPF Write Pulse Width after FF High 12 15 20 25 ns
t
XOL Read/Write to XO Low 12 15 20 25 ns
tXOH Read/Write to XO High 12 15 20 25 ns
t
XI XI Pulse Width
(3)
12 15 20 25 ns
t
XIR XI Recovery Time 8 10 10 10 ns
tXIS XI Set-up Time 8 10 10 10 ns
NOTES:
1. Timings referenced as in AC Test Conditions.
2. Industrial temperature range product for 15ns and 25ns speed grades are available as a standard device.
3. Pulse widths less than minimum value are not allowed.
4. Values guaranteed by design, not currently tested.
5. Only applies to read data flow-through mode
AC ELECTRICAL CHARACTERISTICS
(1)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
5
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
Military Commercial Com'l & Mil.
(2)
Military
(2)
IDT7200L30 IDT7200L35 IDT7200L50
IDT7201LA30 IDT7201LA35 IDT7201LA50
IDT7202LA30 IDT7202LA35 IDT7202LA50 IDT7201LA80
Symbol Parameter Min. Max. Min. Max. Min. Max. Min. Max. Unit
t
S Shift Frequency 25 22.2 15 10 M H z
t
RC Read Cycle Time 40 45 65 100 ns
t
A Access Time 30 35 50 80 ns
t
RR Read Recovery Time 10 10 15 20 ns
tRPW Read Pulse Width
(3)
30 35 50 80 ns
t
RLZ Read Pulse Low to Data Bus at Low Z
(4)
3—3—3—3ns
t
WLZ Write Pulse High to Data Bus at Low Z
(4, 5)
5—5—5—5ns
tDV Data Valid from Read Pulse High 5 5 5 5 ns
t
RHZ Read Pulse High to Data Bus at High Z
(4)
—20—20—30—30ns
t
WC Write Cycle Time 40 45 65 100 ns
tWPW Write Pulse Width
(3)
30 35 50 80 ns
tWR Write Recovery Time 10 10 15 20 ns
tDS Data Set-up Time 18 18 30 40 ns
tDH Data Hold Time 0 0 5 10 ns
tRSC Reset Cycle Time 40 45 65 100 ns
t
RS Reset Pulse Width
(3)
30 35 50 80 ns
tRSS Reset Set-up Time
(4)
30 35 50 80 ns
tRSR Reset Recovery Time 10 10 15 20 ns
tRTC Retransmit Cycle Time 40 45 65 100 ns
tRT Retransmit Pulse Width
(3)
30 35 50 80 ns
tRTS Retransmit Set-up Time
(4)
30 35 50 80 ns
tRTR Retransmit Recovery Time 10 10 15 20 ns
t
EFL Reset to Empty Flag Low 40 45 65 100 ns
tHFH,FFH Reset to Half-Full and Full Flag High 40 45 65 100 ns
tRTF Retransmit Low to Flags Valid 40 45 65 100 ns
tREF Read Low to Empty Flag Low 30 30 45 60 ns
tRFF Read High to Full Flag High 30 30 45 60 ns
tRPE Read Pulse Width after EF High 30 35 50 80 ns
t
WEF Write High to Empty Flag High 30 30 45 60 ns
tWFF Write Low to Full Flag Low 30 30 45 60 ns
tWHF Write Low to Half-Full Flag Low 40 45 65 100 ns
tRHF Read High to Half-Full Flag High 40 45 65 100 ns
tWPF Write Pulse Width after FF High 30 35 50 80 ns
tXOL Read/Write to XO Low —30—35—50—80ns
t
XOH Read/Write to XO High 30 35 50 80 ns
tXI XI Pulse Width
(3)
30 35 50 80 ns
tXIR XI Recovery Time 10 10 10 10 ns
tXIS XI Set-up Time 10 10 15 15 ns
AC ELECTRICAL CHARACTERISTICS
(1)
(Continued)
(Commercial: VCC = 5V ± 10%, TA = 0°C to +70°C; Industrial: VCC = 5V ± 10%, TA = –40°C to +85°C; Military: VCC = 5V ± 10%, TA = –55°C to +125°C)
NOTES:
1. Timings referenced as in AC Test Conditions
2. Military speed grades of 50ns and 80ns are only available for IDT7201LA.
3. Pulse widths less than minimum value are not allowed.
4. Values guaranteed by design, not currently tested.
5. Only applies to read data flow-through mode.
6
COMMERCIAL, INDUSTRIAL AND MILITARY
TEMPERATURE RANGES
IDT7201L/7201LA/7202LA CMOS ASYNCHRONOUS FIFO
256 x 9, 512 x 9 and 1,024 x 9
Device Mode, this pin acts as the retransmit input. The Single Device Mode is
initiated by grounding the Expansion In (XI).
The IDT7200/7201A/7202A can be made to retransmit data when the
Retransmit Enable control (RT) input is pulsed LOW. A retransmit operation will
set the internal read pointer to the first location and will not affect the write pointer.
Read Enable (R) and Write Enable (W) must be in the HIGH state during
retransmit. This feature is useful when less than 256/512/1,024 writes are
performed between resets. The retransmit feature is not compatible with the
Depth Expansion Mode and will affect the Half-Full Flag (HF), depending on
the relative locations of the read and write pointers.
EXPANSION IN (XI)
This input is a dual-purpose pin. Expansion In (XI) is grounded to indicate
an operation in the single device mode. Expansion In (XI) is connected to
Expansion Out (XO) of the previous device in the Depth Expansion or Daisy
Chain Mode.
OUTPUTS:
FULL FLAG (FF)
The Full Flag (FF) will go LOW, inhibiting further write operation, when the
write pointer is one location less than the read pointer, indicating that the
device is full. If the read pointer is not moved after Reset (RS), the Full-Flag
(FF) will go LOW after 256 writes for IDT7200, 512 writes for the IDT7201A and
1,024 writes for the IDT7202A.
EMPTY FLAG (EF)
The Empty Flag (EF) will go LOW, inhibiting further read operations, when
the read pointer is equal to the write pointer, indicating that the device is
empty.
EXPANSION OUT/HALF-FULL FLAG (XO/HF)
This is a dual-purpose output. In the single device mode, when
Expansion In (XI) is grounded, this output acts as an indication of a half-full
memory.
After half of the memory is filled and at the falling edge of the next write
operation, the Half-Full Flag (HF) will be set LOW and will remain set until the
difference between the write pointer and read pointer is less than or equal
to one half of the total memory of the device. The Half-Full Flag (HF) is then
reset by using rising edge of the read operation.
In the Depth Expansion Mode, Expansion In (XI) is connected to Expansion
Out (XO) of the previous device. This output acts as a signal to the next device
in the Daisy Chain by providing a pulse to the next device when the previous
device reaches the last location of memory.
DATA OUTPUTS (Q0 – Q8)
Data outputs for 9-bit wide data. This data is in a high impedance condition
whenever Read (R) is in a HIGH state.
SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D0 – D8)
Data inputs for 9-bit wide data.
CONTROLS:
RESET (RS)
Reset is accomplished whenever the Reset (RS) input is taken to a LOW
state. During reset, both internal read and write pointers are set to the first
location. A reset is required after power up before a write operation can take
place. Both the Read Enable (R) and Write Enable (W) inputs must be
in the HIGH state during the window shown in Figure 2, (i.e., t
RSS
before the rising edge of RS) and should not change until tRSR after
the rising edge of RS. Half-Full Flag (HF) will be reset to HIGH after
Reset (RS).
WRITE ENABLE (W)
A write cycle is initiated on the falling edge of this input if the Full Flag (FF)
is not set. Data set-up and hold times must be adhered to with respect to the rising
edge of the Write Enable (W). Data is stored in the RAM array sequentially and
independently of any on-going read operation.
After half of the memory is filled and at the falling edge of the next write
operation, the Half-Full Flag (HF) will be set to LOW and will remain set until the
difference between the write pointer and read pointer is less than or equal to
one half of the total memory of the device. The Half-Full Flag (HF) is then reset
by the rising edge of the read operation.
To prevent data overflow, the Full Flag (FF) will go LOW, inhibiting further
write operations. Upon the completion of a valid read operation, the Full
Flag (FF) will go HIGH after tRFF, allowing a valid write to begin. When the FIFO
is full, the internal write pointer is blocked from W, so external changes in W will
not affect the FIFO when it is full.
READ ENABLE (R)
A read cycle is initiated on the falling edge of the Read Enable (R) provided
the Empty Flag (EF) is not set. The data is accessed on a First-In/First-Out basis,
independent of any ongoing write operations. After Read Enable (R) goes
HIGH, the Data Outputs (Q0 – Q8) will return to a high impedance condition until
the next Read operation. When all data has been read from the FIFO, the Empty
Flag (EF) will go LOW, allowing the “final” read cycle but inhibiting further read
operations with the data outputs remaining in a high impedance state. Once a
valid write operation has been accomplished, the Empty Flag (EF) will go HIGH
after tWEF and a valid Read can then begin. When the FIFO is empty, the internal
read pointer is blocked from R so external changes in R will not affect the FIFO
when it is empty.
FIRST LOAD/RETRANSMIT (FL/RT)
This is a dual-purpose input. In the Depth Expansion Mode, this pin is
grounded to indicate that it is the first loaded (see Operating Modes). In the Single

7201LA12SOG8

Mfr. #:
Manufacturer:
IDT
Description:
FIFO 512 X 9 CMOS PARALLEL FIF
Lifecycle:
New from this manufacturer.
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