Table 11: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
Parameter Symbol
gDDR3-1600 gDDR3-1800
Unit NotesMin Max Min Max
R
TT
synchronous turn-off delay ODTL off CWL + AL - 2CK CK 40
R
TT
turn-on from ODTL on reference
t
AON –250 250 –225 225 ps 23, 38
R
TT
turn-off from ODTL off reference
t
AOF 0.3 0.7 0.3 0.7 CK 39, 40
Asynchronous R
TT
turn-on delay
(power-down with DLL off)
t
AONPD MIN = 2; MAX = 8.5 ns 38
Asynchronous R
TT
turn-off delay
(power-down with DLL off)
t
AOFPD MIN = 2; MAX = 8.5 ns 40
ODT HIGH time with WRITE command and BL8 ODTH8 MIN = 6; MAX = N/A CK
ODT HIGH time without WRITE command or
with WRITE command and BC4
ODTH4 MIN = 4; MAX = N/A CK
Dynamic ODT Timing
R
TT,nom
-to-R
TT(WR)
change skew ODTLcnw WL - 2CK CK
R
TT(WR)
-to-R
TT,nom
change skew - BC4 ODTLcnw4 4CK + ODTLoff CK
R
TT(WR)
-to-R
TT,nom
change skew - BL8 ODTLcnw8 6CK + ODTLoff CK
R
TT
dynamic change skew
t
ADC 0.3 0.7 0.3 0.7 CK 39
Write Leveling Timing
First DQS, DQS# rising edge
t
WLMRD 40 – 40 – CK
DQS, DQS# delay
t
WLDQSEN 25 – 25 – CK
Write leveling setup from rising CK, CK# cross-
ing to rising DQS, DQS# crossing
t
WLS 195 – 165 – ps
Write leveling hold from rising DQS, DQS#
crossing to rising CK, CK# crossing
t
WLH 195 – 165 – ps
Write leveling output delay
t
WLO 0 9 0 7.5 ns
Write leveling output error
t
WLOE 0 2 0 2 ns
Notes:
1. Parameters are applicable with 0°C ≤ T
C
≤ 115°C and V
DD
/V
DDQ
= 1.5V ±0.075V.
2. All voltages are referenced to V
SS
.
3. Output timings are only valid for R
ON34
output buffer selection.
4. The unit
t
CK (AVG) represents the actual
t
CK (AVG) of the input clock under operation.
The unit CK represents one clock cycle of the input clock, counting the actual clock
edges.
5. AC timing and I
DD
tests may use a V
IL
-to-V
IH
swing of up to 900mV in the test environ-
ment, but input timing is still referenced to V
REF
(except
t
IS,
t
IH,
t
DS, and
t
DH use the
AC/DC trip points, and CK, CK# and DQS, DQS# use their crossing points). The minimum
slew rate for the input signals used to test the device is 1 V/ns for single-ended inputs
and 2 V/ns for differential inputs in the range between V
IL(AC)
and V
IH(AC)
.
6. All timings that use time-based values (ns, µs, ms) should use
t
CK (AVG) to determine the
correct number of clocks (this table uses CK or
t
CK [AVG] interchangeably). In the case of
noninteger results, all minimum limits are to be rounded up to the nearest whole inte-
ger, and all maximum limits are to be rounded down to the nearest whole integer.
4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions
CCMTD-1005363231-10344
ddr3_4gb_graphics_addendum 091.pdf - Rev. A 05/16 EN
21
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