Table 11: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
Parameter Symbol
gDDR3-1600 gDDR3-1800
Unit NotesMin Max Min Max
Write recovery time
t
WR 15 N/A 15 N/A ns 31, 32,
33
Delay from start of internal WRITE transaction
to internal READ command
t
WTR MIN = greater of 4CK or 7.5ns; MAX =
N/A
CK 31, 34
READ-to-PRECHARGE time
t
RTP MIN = greater of 4CK or 7.5ns; MAX =
N/A
CK 31, 32
CAS#-to-CAS# command delay
t
CCD MIN = 4CK; MAX = N/A CK
Auto precharge write recovery + precharge
time
t
DAL MIN = WR +
t
RP/
t
CK (AVG); MAX = N/A CK
MODE REGISTER SET command cycle time
t
MRD MIN = 4CK; MAX = N/A CK
MODE REGISTER SET command update delay
t
MOD MIN = greater of 12CK or 15ns; MAX =
N/A
CK
MULTIPURPOSE REGISTER READ burst end to
mode register set for multipurpose register exit
t
MPRR MIN = 1CK; MAX = N/A CK
Calibration Timing
ZQCL command: Long
calibration time
POWER-UP and RE-
SET operation
t
ZQ
INIT
512 512 CK
Normal operation
t
ZQ
OPER
256 256 CK
ZQCS command: Short calibration time
t
ZQCS 64 64 CK
Initialization and Reset Timing
Exit reset from CKE HIGH to a valid command
t
XPR MIN = greater of 5CK or
t
RFC + 10ns;
MAX = N/A
CK
Begin power supply ramp to power supplies
stable
t
VDDPR MIN = N/A; MAX = 200 ms
RESET# LOW to power supplies stable
t
RPS MIN = 0; MAX = 200 ms
RESET# LOW to I/O and R
TT
High-Z
t
IOZ MIN = N/A; MAX = 20 ns 35
Refresh Timing
REFRESH-to-ACTIVATE or REFRESH
command period
t
RFC MIN = 260; MAX = 70,200 ns
Maximum refresh
period
T
C
85°C 64 (1X) ms 36
T
C
> 85°C 32 (2X) ms 36
Maximum average
periodic refresh
T
C
85°C
t
REFI 7.8 (64ms/8192) µs 36
T
C
> 85°C 3.9 (32ms/8192) µs 36
Self Refresh Timing
Exit self refresh to commands not requiring a
locked DLL
t
XS MIN = greater of 5CK or
t
RFC + 10ns;
MAX = N/A
CK
Exit self refresh to commands requiring a
locked DLL
t
XSDLL MIN =
t
DLLK (MIN); MAX = N/A CK 28
4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions
CCMTD-1005363231-10344
ddr3_4gb_graphics_addendum 091.pdf - Rev. A 05/16 EN
19
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Table 11: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
Parameter Symbol
gDDR3-1600 gDDR3-1800
Unit NotesMin Max Min Max
Minimum CKE low pulse width for self refresh
entry to self refresh exit timing
t
CKESR MIN =
t
CKE (MIN) + CK; MAX = N/A CK
Valid clocks after self refresh entry or power-
down entry
t
CKSRE MIN = greater of 5CK or 10ns; MAX =
N/A
CK
Valid clocks before self refresh exit,
power-down exit, or reset exit
t
CKSRX MIN = greater of 5CK or 10ns; MAX =
N/A
CK
Power-Down Timing
CKE MIN pulse width
t
CKE (MIN) Greater of 3CK or
5.625ns
Greater of 3CK or
5ns
CK
Command pass disable delay
t
CPDED MIN = 1;
MAX = N/A
CK
Power-down entry to power-down exit timing
t
PD MIN =
t
CKE (MIN); MAX = 9 ×
t
REFI CK
Begin power-down period prior to CKE regis-
tered HIGH
t
ANPD WL - 1CK CK
Power-down entry period: ODT either synchro-
nous or asynchronous
PDE Greater of
t
ANPD or
t
RFC - REFRESH
command to CKE LOW time
CK
Power-down exit period: ODT either
synchronous or asynchronous
PDX
t
ANPD +
t
XPDLL CK
Power-Down Entry Minimum Timing
ACTIVATE command to power-down entry
t
ACTPDEN MIN = 1 CK
PRECHARGE/PRECHARGE ALL command to
power-down entry
t
PRPDEN MIN = 1 CK
REFRESH command to power-down entry
t
REFPDEN MIN = 1 CK 37
MRS command to power-down entry
t
MRSPDEN MIN =
t
MOD (MIN) CK
READ/READ with auto precharge command to
power-down entry
t
RDPDEN MIN = RL + 4 + 1 CK
WRITE command to
power-down entry
BL8 (OTF, MRS)
BC4OTF
t
WRPDEN MIN = WL + 4 +
t
WR/
t
CK (AVG) CK
BC4MRS
t
WRPDEN MIN = WL + 2 +
t
WR/
t
CK (AVG) CK
WRITE with auto pre-
charge command to
power-down entry
BL8 (OTF, MRS)
BC4OTF
t
WRAPDEN MIN = WL + 4 + WR + 1 CK
BC4MRS
t
WRAPDEN MIN = WL + 2 + WR + 1 CK
Power-Down Exit Timing
DLL on, any valid command, or DLL off to com-
mands not requiring locked DLL
t
XP MIN = greater of 3CK or 6ns; MAX =
N/A
CK
Precharge power-down with DLL off to com-
mands requiring a locked DLL
t
XPDLL MIN = greater of 10CK or 24ns; MAX =
N/A
CK 28
ODT Timing
R
TT
synchronous turn-on delay ODTL on CWL + AL - 2CK CK 38
4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions
CCMTD-1005363231-10344
ddr3_4gb_graphics_addendum 091.pdf - Rev. A 05/16 EN
20
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Table 11: Electrical Characteristics and AC Operating Conditions for Speed Extensions (Continued)
Notes 1–8 apply to the entire table
Parameter Symbol
gDDR3-1600 gDDR3-1800
Unit NotesMin Max Min Max
R
TT
synchronous turn-off delay ODTL off CWL + AL - 2CK CK 40
R
TT
turn-on from ODTL on reference
t
AON –250 250 –225 225 ps 23, 38
R
TT
turn-off from ODTL off reference
t
AOF 0.3 0.7 0.3 0.7 CK 39, 40
Asynchronous R
TT
turn-on delay
(power-down with DLL off)
t
AONPD MIN = 2; MAX = 8.5 ns 38
Asynchronous R
TT
turn-off delay
(power-down with DLL off)
t
AOFPD MIN = 2; MAX = 8.5 ns 40
ODT HIGH time with WRITE command and BL8 ODTH8 MIN = 6; MAX = N/A CK
ODT HIGH time without WRITE command or
with WRITE command and BC4
ODTH4 MIN = 4; MAX = N/A CK
Dynamic ODT Timing
R
TT,nom
-to-R
TT(WR)
change skew ODTLcnw WL - 2CK CK
R
TT(WR)
-to-R
TT,nom
change skew - BC4 ODTLcnw4 4CK + ODTLoff CK
R
TT(WR)
-to-R
TT,nom
change skew - BL8 ODTLcnw8 6CK + ODTLoff CK
R
TT
dynamic change skew
t
ADC 0.3 0.7 0.3 0.7 CK 39
Write Leveling Timing
First DQS, DQS# rising edge
t
WLMRD 40 40 CK
DQS, DQS# delay
t
WLDQSEN 25 25 CK
Write leveling setup from rising CK, CK# cross-
ing to rising DQS, DQS# crossing
t
WLS 195 165 ps
Write leveling hold from rising DQS, DQS#
crossing to rising CK, CK# crossing
t
WLH 195 165 ps
Write leveling output delay
t
WLO 0 9 0 7.5 ns
Write leveling output error
t
WLOE 0 2 0 2 ns
Notes:
1. Parameters are applicable with 0°C T
C
115°C and V
DD
/V
DDQ
= 1.5V ±0.075V.
2. All voltages are referenced to V
SS
.
3. Output timings are only valid for R
ON34
output buffer selection.
4. The unit
t
CK (AVG) represents the actual
t
CK (AVG) of the input clock under operation.
The unit CK represents one clock cycle of the input clock, counting the actual clock
edges.
5. AC timing and I
DD
tests may use a V
IL
-to-V
IH
swing of up to 900mV in the test environ-
ment, but input timing is still referenced to V
REF
(except
t
IS,
t
IH,
t
DS, and
t
DH use the
AC/DC trip points, and CK, CK# and DQS, DQS# use their crossing points). The minimum
slew rate for the input signals used to test the device is 1 V/ns for single-ended inputs
and 2 V/ns for differential inputs in the range between V
IL(AC)
and V
IH(AC)
.
6. All timings that use time-based values (ns, µs, ms) should use
t
CK (AVG) to determine the
correct number of clocks (this table uses CK or
t
CK [AVG] interchangeably). In the case of
noninteger results, all minimum limits are to be rounded up to the nearest whole inte-
ger, and all maximum limits are to be rounded down to the nearest whole integer.
4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions
CCMTD-1005363231-10344
ddr3_4gb_graphics_addendum 091.pdf - Rev. A 05/16 EN
21
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.

MT41J256M16LY-091G:N

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Micron
Description:
IC DRAM 4G PARALLEL 1GHZ 96FBGA
Lifecycle:
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