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MT41J256M16LY-091G:N

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7. Strobe or DQS diff refers to the DQS and DQS# differential crossing point when DQS is
the rising edge. Clock or CK refers to the CK and CK# differential crossing point when
CK is the rising edge.
8. This output load is used for all AC timing (except ODT reference timing) and slew rates.
The actual test load may be different. The output signal voltage reference point is
V
DDQ
/2 for single-ended signals and the crossing point for differential signals.
9. When operating in DLL disable mode, Micron does not warrant compliance with normal
mode timings or functionality.
10. The clock’s
t
CK (AVG) is the average clock over any 200 consecutive clocks and
t
CK (AVG)
MIN is the smallest clock rate allowed, with the exception of a deviation due to clock
jitter. Input clock jitter is allowed provided it does not exceed values specified and must
be of a random Gaussian distribution in nature.
11. Spread spectrum is not included in the jitter specification values. However, the input
clock can accommodate spread-spectrum at a sweep rate in the range of 20–60 kHz with
an additional 1% of
t
CK (AVG) as a long-term jitter component; however, the spread
spectrum may not use a clock rate below
t
CK (AVG) MIN.
12. The clock’s
t
CH (AVG) and
t
CL (AVG) are the average half clock period over any 200 con-
secutive clocks and is the smallest clock half period allowed, with the exception of a de-
viation due to clock jitter. Input clock jitter is allowed provided it does not exceed values
specified and must be of a random Gaussian distribution in nature.
13. The period jitter (
t
JIT
PER
) is the maximum deviation in the clock period from the average
or nominal clock. It is allowed in either the positive or negative direction.
14.
t
CH (ABS) is the absolute instantaneous clock high pulse width as measured from one
rising edge to the following falling edge.
15.
t
CL (ABS) is the absolute instantaneous clock low pulse width as measured from one fall-
ing edge to the following rising edge.
16. The cycle-to-cycle jitter
t
JIT
CC
is the amount the clock period can deviate from one cycle
to the next. It is important to keep cycle-to-cycle jitter at a minimum during the DLL
locking time.
17. The cumulative jitter error
t
ERRnPER, where n is the number of clocks between 2 and 50,
is the amount of clock time allowed to accumulate consecutively away from the average
clock over n number of clock cycles.
18.
t
DS (base) and
t
DH (base) values are for a single-ended 1 V/ns DQ slew rate and 2 V/ns
differential DQS, DQS# slew rate.
19. These parameters are measured from a data signal (DM, DQ0, DQ1, and so forth) transi-
tion edge to its respective data strobe signal (DQS, DQS#) crossing.
20. The setup and hold times are listed converting the base specification values (to which
derating tables apply) to V
REF
when the slew rate is 1 V/ns. These values, with a slew rate
of 1 V/ns, are for reference only.
21. When the device is operated with input clock jitter, this parameter needs to be derated
by the actual
t
JIT
PER
(larger of
t
JIT
PER
(MIN) or
t
JIT
PER
(MAX) of the input clock (output
deratings are relative to the SDRAM input clock).
22. Single-ended signal parameter.
23. The DRAM output timing is aligned to the nominal or average clock. Most output pa-
rameters must be derated by the actual jitter error when input clock jitter is present,
even when within specification. This results in each parameter becoming larger. The fol-
lowing parameters are required to be derated by subtracting
t
ERR
10PER
(MAX):
t
DQSCK
(MIN),
t
LZ(DQS) MIN,
t
LZ(DQ) MIN, and
t
AON (MIN). The following parameters are re-
quired to be derated by subtracting
t
ERR
10PER
(MIN):
t
DQSCK (MAX),
t
HZ (MAX),
t
LZ
(DQS) MAX,
t
LZ (DQ) MAX, and
t
AON (MAX). The parameter
t
RPRE (MIN) is derated by
subtracting
t
JIT
PER
(MAX), while
t
RPRE (MAX) is derated by subtracting
t
JIT
PER
(MIN).
24. The maximum preamble is bound by
t
LZDQS (MAX).
25. These parameters are measured from a data strobe signal (DQS, DQS#) crossing to its re-
spective clock signal (CK, CK#) crossing. The specification values are not affected by the
4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions
CCMTD-1005363231-10344
ddr3_4gb_graphics_addendum 091.pdf - Rev. A 05/16 EN
22
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
amount of clock jitter applied because these are relative to the clock signal crossing.
These parameters should be met whether clock jitter is present.
26. The
t
DQSCK (DLL_DIS) parameter begins CL + AL - 1 cycles after the READ command.
27. The maximum postamble is bound by
t
HZDQS (MAX).
28. Commands requiring a locked DLL are READ (and RDAP) and synchronous ODT com-
mands. In addition, after any change of latency
t
XPDLL, timing must be met.
29.
t
IS (base) and
t
IH (base) values are for a single-ended 1 V/ns control/command/address
slew rate and 2 V/ns CK, CK# differential slew rate.
30. These parameters are measured from a command/address signal transition edge to its
respective clock (CK, CK#) signal crossing. The specification values are not affected by
the amount of clock jitter applied as the setup and hold times are relative to the clock
signal crossing that latches the command/address. These parameters should be met
whether clock jitter is present.
31. For these parameters, the DDR3 SDRAM device supports
t
nPARAM (nCK) = RU(
t
PARAM
[ns]/
t
CK[AVG] [ns]), assuming all input clock jitter specifications are satisfied. For exam-
ple, the device will support
t
nRP (nCK) = RU(
t
RP/
t
CK[AVG]) if all input clock jitter specifi-
cations are met. This means that for DDR3-800 6-6-6, of which
t
RP = 15ns, the device will
support
t
nRP = RU(
t
RP/
t
CK[AVG]) = 6 as long as the input clock jitter specifications are
met. That is, the PRECHARGE command at T0 and the ACTIVATE command at T0 + 6 are
valid even if six clocks are less than 15ns due to input clock jitter.
32. During READs and WRITEs with auto precharge, the DDR3 SDRAM will hold off the in-
ternal PRECHARGE command until
t
RAS (MIN) has been satisfied.
33. When operating in DLL disable mode, the greater of 4CK or 15ns is satisfied for
t
WR.
34. The start of the write recovery time is defined as follows:
• For BL8 (fixed by MRS and OTF): Rising clock edge four clock cycles after WL
• For BC4 (OTF): Rising clock edge four clock cycles after WL
• For BC4 (fixed by MRS): Rising clock edge two clock cycles after WL
35. RESET# should be LOW as soon as power starts to ramp to ensure the outputs are in
High-Z. Until RESET# is LOW, the outputs are at risk of driving and could result in exces-
sive current, depending on bus activity.
36. The refresh period is 64ms when T
C
is less than or equal to 85°C. This equates to an aver-
age refresh rate of 7.8125µs. However, nine REFRESH commands should be asserted at
least once every 70.3µs. When T
C
is greater than 85°C, the refresh period is 32ms.
37. Although CKE is allowed to be registered LOW after a REFRESH command when
t
REFPDEN (MIN) is satisfied, there are cases where additional time such as
t
XPDLL (MIN)
is required.
38. ODT turn-on time MIN is when the device leaves High-Z and ODT resistance begins to
turn on. ODT turn-on time maximum is when the ODT resistance is fully on.
39. Half-clock output parameters must be derated by the actual
t
ERR
10PER
and
t
JIT
DTY
when
input clock jitter is present. This results in each parameter becoming larger. The parame-
ters
t
ADC (MIN) and
t
AOF (MIN) are each required to be derated by subtracting both
t
ERR
10PER
(MAX) and
t
JIT
DTY
(MAX). The parameters
t
ADC (MAX) and
t
AOF (MAX) are re-
quired to be derated by subtracting both
t
ERR
10PER
(MAX) and
t
JIT
DTY
(MAX).
40. ODT turn-off time minimum is when the device starts to turn off ODT resistance. ODT
turn-off time maximum is when the DRAM buffer is in High-Z.
41. Pulse width of an input signal is defined as the width between the first crossing of
V
REF(DC)
and the consecutive crossing of V
REF(DC)
.
42. Should the clock rate be larger than
t
RFC (MIN), an AUTO REFRESH command should
have at least one NOP command between it and another AUTO REFRESH command. Ad-
ditionally, if the clock rate is slower than 40ns (25 MHz), all REFRESH commands should
be followed by an AUTO PRECHARGE command.
4Gb: x16 gDDR3 SDRAM Graphics Addendum
Electrical Characteristics and AC Operating Conditions
CCMTD-1005363231-10344
ddr3_4gb_graphics_addendum 091.pdf - Rev. A 05/16 EN
23
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Command and Address Setup, Hold, and Derating
The total
t
IS (setup time) and
t
IH (hold time) required is calculated by adding the data
sheet
t
IS (base) and
t
IH (base) values to the Δ
t
IS and Δ
t
IH derating values, respectively.
Example:
t
IS (total setup time) =
t
IS (base) + Δ
t
IS. For a valid transition, the input signal
has to remain above/below V
IH(AC)
/V
IL(AC)
for some time
t
VAC.
Although the total setup time for slow slew rates might be negative (for example, a valid
input signal will not have reached V
IH(AC)
/V
IL(AC)
at the time of the rising clock transi-
tion), a valid input signal is still required to complete the transition and to reach
V
IH(AC)
/V
IL(AC)
.
Setup (
t
IS) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of V
REF(DC)
and the first crossing of V
IH(AC)min
. Setup (
t
IS) nominal slew rate
for a falling signal is defined as the slew rate between the last crossing of V
REF(DC)
and
the first crossing of V
IL(AC)max
. If the actual signal is always earlier than the nominal slew
rate line between the shaded V
REF(DC)
-to-AC region, use the nominal slew rate for derat-
ing value. If the actual signal is later than the nominal slew rate line anywhere between
the shaded V
REF(DC)
-to-AC region, the slew rate of a tangent line to the actual signal
from the AC level to the DC level is used for derating value.
Hold (
t
IH) nominal slew rate for a rising signal is defined as the slew rate between the
last crossing of V
IL(DC)max
and the first crossing of V
REF(DC)
. Hold (
t
IH) nominal slew rate
for a falling signal is defined as the slew rate between the last crossing of V
IH(DC)min
and
the first crossing of V
REF(DC)
. If the actual signal is always later than the nominal slew
rate line between the shaded DC-to-V
REF(DC)
region, use the nominal slew rate for derat-
ing value. If the actual signal is earlier than the nominal slew rate line anywhere be-
tween the shaded DC-to-V
REF(DC)
region, the slew rate of a tangent line to the actual sig-
nal from the DC level to the V
REF(DC)
level is used for derating value.
Table 12: Command and Address Setup and Hold Values Referenced at 1 V/ns – AC/DC-Based
Symbol gDDR3-1600 gDDR3-1800 gDDR3-2000 gDDR3-2200 Unit Reference
t
IS (base) AC175 65 45 – – ps V
IH(AC)
/V
IL(AC)
t
IS (base) AC150 190 170 – – ps V
IH(AC)
/V
IL(AC)
t
IS (base) AC135 – – 65 65 ps V
IH(AC)
/V
IL(AC)
t
IS (base) AC125 – – 150 150 ps V
IH(AC)
/V
IL(AC)
t
IH (base) DC100 140 120 100 100 ps V
IH(DC)
/V
IL(DC)
4Gb: x16 gDDR3 SDRAM Graphics Addendum
Command and Address Setup, Hold, and Derating
CCMTD-1005363231-10344
ddr3_4gb_graphics_addendum 091.pdf - Rev. A 05/16 EN
24
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
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MT41J256M16LY-091G:N

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Buy MT41J256M16LY-091G:N
Manufacturer:
Micron
Description:
IC DRAM 4G PARALLEL 1GHZ 96FBGA
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