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IR2301SPBF
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
IR2301
(
S)
&
(
PbF)
10
www.irf.com
0
100
200
300
400
500
-
50
-
25
0
25
50
75
100
125
T
em
per
at
ur
e (
o
C)
Offset Supply Leakage Current (
A)
Ma
x
.
0
100
200
300
400
500
100
200
300
400
500
600
O
f
f
s
et
S
up
pl
y
V
olt
age (
V
)
Offset Supply Leakage Current (
A)
Ma
x
.
0
50
100
150
200
-
50
-
25
0
25
50
75
100
12
5
T
em
per
atur
e (
o
C)
Quiescent V
BS
Supply Current (
A)
Mi
n.
Ty
p.
Ma
x
.
0
50
100
150
200
51
0
1
5
2
0
V
BS
S
uppl
y
Vo
l
t
age (
V
)
Quiescent V
BS
Supply Current (
A)
Ty
p.
Ma
x
.
Mi
n.
Figure 12A. Offset Supply Leakage Current
vs. T
emperature
Figure 12B. Offset Supply Leakage Current
vs. Supply V
oltage
Figure 13A. Quiescent V
BS
Supply Current
vs. T
emperature
Figure 13B. Quiescent V
BS
Supply Current
vs. Supply V
olta
ge
IR2301
(
S
)
&
(
PbF)
www.irf.com
11
0
100
200
300
400
-
50
-
25
0
25
50
75
100
125
T
em
per
atur
e (
o
C)
Quiescent V
CC
Supply Current (
A)
Mi
n.
Ty
p.
Ma
x
.
0
100
200
300
400
51
0
1
5
2
0
V
CC
S
uppl
y
Vol
t
age (
V
)
Quiescent V
CC
Supply Current (
A)
Ty
p.
Ma
x
.
Mi
n.
0
10
20
30
40
50
60
-
5
0
-
2
50
2
55
07
5
1
0
0
1
2
5
T
em
per
atur
e (
o
C)
Logic "1" Input Bias Current (
A)
Ty
p.
Ma
x
.
Figure 14A. Quiescent V
CC
Supply Current
vs. T
emperature
Figure 14B. Quiescent V
CC
Supply Current
vs. V
CC
Supply V
oltage
Figure 15A. Logic “1” Input Bias Current
vs. T
emperature
Figure 15B. Logic “1” Input Bias Current
vs. Supply V
olta
ge
0
10
20
30
40
50
51
0
1
5
2
0
S
uppl
y
V
ol
t
age (
V
)
Logic "1" Input Bias Current (
A)
Ty
p.
Ma
x
.
IR2301
(
S)
&
(
PbF)
12
www.irf.com
0
1
2
3
4
5
-
5
0-
2
5
0
2
5
5
0
7
51
0
0
1
2
5
T
em
per
atur
e (
o
C)
Logic "0" Input Bias Current (
A)
Ma
x
.
0
1
2
3
4
5
51
0
1
5
2
0
S
uppl
y
V
ol
t
age (
V
)
Logic "0" Input Bias Current (
A)
Ma
x
.
2
3
4
5
6
-
5
0-
2
5
0
2
5
5
0
7
51
0
0
1
2
5
T
em
per
atur
e (
o
C)
V
CC
and V
BS
Undervoltage Threshold (+) (V)
Mi
n.
Ty
p.
Ma
x
.
2
3
4
5
6
-
50
-
25
0
25
50
75
100
125
T
em
per
at
ur
e (
o
C)
V
CC
and V
BS
Undervoltage Threshold (-) (V)
Mi
n.
Ty
p.
Ma
x
.
Figure 16A. Logic “0” Input Bias Current
vs. T
emperature
Figure 16B. Logic “0” Input Bias Currentt
vs. Supply V
oltage
Figure 17. V
CC
and V
BS
Undervoltage Threshold (+)
vs. T
emperature
Figure 18. V
CC
and V
BS
Undervoltage Threshold (-)
vs. T
emperature
P1-P3
P4-P6
P7-P9
P10-P12
P13-P15
P16-P18
IR2301SPBF
Mfr. #:
Buy IR2301SPBF
Manufacturer:
Infineon Technologies
Description:
Gate Drivers HI LO SIDE DRVR 600V 5V to 20V
Lifecycle:
New from this manufacturer.
Delivery:
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