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8. Security Fuses
There are three fuses on the device that must be blown during the device personalization process. Each fuse locks certain
portions of the configuration memory as OTP memory. Fuses are designed for the module manufacturer, card manufacturer
and card issuer and should be blown in sequence, although all programming of the device and blowing of the fuses may be
performed at one final step.
9. Protocol selection
The AT88SC0104C supports two different communication protocols.
Smart Card Applications:
The asynchronous T = 0 protocol defined by ISO 7816-3 is used for compatibility with the industry’s standard smart
card readers
Embedded Applications:
A 2-wire serial interface is used for fast and efficient communication with logic or controllers
The power-up sequence determines which of the two communication protocols will be used.
9.1 Asynchronous T = 0 Protocol
This power-up sequence complies with ISO 7816-3 for a cold reset in smart card applications.
V
CC
goes high; RST, I/O-SDA and CLK-SCL are low
Set I/O-SDA in receive mode
Provide a clock signal to CLK-SCL
RST goes high after 400 clock cycles
The device will respond with a 64-bit ATR code, including historical bytes to indicate the memory density within the
CryptoMemory family. Once the asynchronous mode has been selected, it is not possible to switch to the synchronous mode
without powering off the device.
Figure 9-1. Asynchronous T = 0 Protocol (Gemplus Patent)
V
cc
I/O-SDA
RST
CLK-SCL
ATR
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9.2 Synchronous 2-wire Serial Interface
The synchronous mode is the default after powering up V
CC
due to an internal pull-up on RST. For embedded applications
using CryptoMemory in standard plastic packages, this is the only communication protocol.
Power-up V
CC
, RST goes high also
After stable V
CC
, CLK-SCL and I/O-SDA may be driven
Figure 9-2. Synchronous 2-wire Protocol
Note: Five clock pulses must be sent before the first command is issued
10. Communication Security Modes
Communications between the device and host operate in three basic modes. Standard mode is the default mode for the
device after power-up. Authentication mode is activated by a successful authentication sequence. Encryption mode is
activated by a successful encryption activation following a successful authentication.
Table 10-1. Communication Security Modes
(1)
Mode Configuration Data User Data Passwords Data Integrity Check
Standard clear clear clear MDC(1)
Authentication clear clear encrypted MAC(1)
Encryption clear encrypted encrypted MAC(1)
Note: 1. Configuration data include viewable areas of the configuration zone except the passwords:
MDC: Modification Detection Code
MAC: Message Authentication Code
V
cc
I/O-SDA
RST
CLK-SCL
1
2
3
4 5
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11. Security Options
11.1 Anti-tearing
In the event of a power loss during a write cycle, the integrity of the device’s stored data may be recovered. This function is
optional: the host may choose to activate the anti-tearing function, depending on application requirements. When anti-tearing
is active, write commands take longer to execute, since more write cycles are required to complete them, and data are limited
to eight bytes.
Data are written first to a buffer zone in EEPROM instead of the intended destination address, but with the same access
conditions. The data are then written in the required location. If this second write cycle is interrupted due to a power loss, the
device will automatically recover the data from the system buffer zone at the next power-up.
In 2-wire mode, the host is required to perform ACK polling for up to 8mS after write commands when anti-tearing is active. At
power-up, the host is required to perform ACK polling, in some cases for up to 2mS, in the event that the device needs to carry
out the data recovery process.
11.2 Write Lock
If a user zone is configured in the write lock mode, the lowest address byte of an 8-byte page constitutes a write access byte
for the bytes of that page.
Example: The write lock byte at $080 controls the bytes from $080 to $087
Figure 11-1. Write Lock Example
Address $0 $1 $2 $3 $4 $5 $6 $7
$080 11011001 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx
locked locked locked
The write lock byte may also be locked by writing its least significant (rightmost) bit to “0”. Moreover, when write lock mode is
activated, the write lock byte can only be programmed that is, bits written to “0” cannot return to “1”.
In the write lock configuration, only one byte can be written at a time. Even if several bytes are received, only the first byte will
be taken into account by the device.

AT88SC0104C-MJ

Mfr. #:
Manufacturer:
Microchip Technology / Atmel
Description:
EEPROM CRYPTO Memory 1Kbit, 4zones
Lifecycle:
New from this manufacturer.
Delivery:
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