AT91SAM9N12-CU

UTXDx UARTx Transmit Data Output

URXDx UARTx Receive Data Input

Synchronous Serial Controller - SSC

TD SSC Transmit Data Output

RD SSC Receive Data Input

TK SSC Transmit Clock I/O

RK SSC Receive Clock I/O

TF SSC Transmit Frame Sync I/O

SPIx_MISO Master In Slave Out I/O

SPIx_MOSI Master Out Slave In I/O

SPIx_SPCK SPI Serial Clock I/O

SPIx_NPCS0 SPI Peripheral Chip Select 0 I/O Low

SPIx_NPCS1-

SPIx_NPCS3

USB Device Full Speed Port - UDP

DDP USB Device Data + Analog

DDM USB Device Data - Analog

USB Host Full Speed Port - UHP

HDM USB Host Data - Analog

LCD Controller - LCDC

LCDDAT 0-23 LCD Data Bus Output

LCDVSYNC LCD Vertical Synchronization Output

LCDHSYNC LCD Horizontal Synchronization Output

LCDPCK LCD Pixel Clock Output

Table 3-1. Signal Description List (Continued)

Signal Name Function Type Active Level

When “Reset State” is stated, the configuration is defined by the “Reset State” column of the Pin Description table.

LCDDEN LCD Data Enable Output

LCDPWM LCD Contrast Control Output

LCDDISP LCD Display Enable Output

Analog-to-Digital Converter - ADC

AD0

Top/Upper Left Channel Analog

AD1

Bottom/Upper Right Channel Analog

AD4

Lower Right Channel Analog

AD5-AD11 7 Analog Inputs Analog

ADTRG ADC Trigger Input

ADVREF ADC Reference Analog

Table 3-1. Signal Description List (Continued)

Signal Name Function Type Active Level

4.1 Mechanical Overview of the 217-ball BGA Package

Figure 4-1 shows the orientation of the 217-ball BGA Package