24AA1026/24LC1026/24FC1026
DS20002270E-page 4 2011-2015 Microchip Technology Inc.
9TSU:DAT Data Input Setup Time 250 ns 1.7V VCC 2.5V
250 ns 2.5V VCC 4.5V, E-temp
100 ns 2.5V V
CC 5.5V
100 ns 1.8V VCC 2.5V (24FC1026)
100 ns 2.5V VCC 5.5V (24FC1026)
10 T
SU:STO Stop Condition Setup
Time
4000 ns 1.7V VCC 2.5V
4000 ns 2.5V VCC 4.5V, E-temp
600 ns 2.5V VCC 5.5V
600 ns 1.8V V
CC 2.5V (24FC1026)
250 ns 2.5V V
CC 5.5V (24FC1026)
11 TSU:WP WP Setup Time 4000 ns 1.7V VCC 2.5V
4000 ns 2.5V V
CC 4.5V, E-temp
600 ns 2.5V VCC 5.5V
600 ns 1.8V VCC 2.5V (24FC1026)
600 ns 2.5V V
CC 5.5V (24FC1026)
12 THD:WP WP Hold Time 4700 ns 1.7V VCC 2.5V
4700 ns 2.5V VCC 4.5V, E-temp
1300 ns 2.5V V
CC 5.5V
1300 ns 1.8V VCC 2.5V (24FC1026)
1300 ns 2.5V VCC 5.5V (24FC1026)
13 T
AA Output Valid from Clock
(Note 2)
—3500ns1.7V VCC 2.5V
—3500ns2.5V VCC 4.5V, E-temp
900 ns 2.5V VCC 5.5V
900 ns 1.8V V
CC 2.5V (24FC1026)
400 ns 2.5V VCC 5.5V (24FC1026)
14
TBUF
Bus Free Time: bus time
must be free before a new
transmission can start
4700 ns 1.7V VCC 2.5V
4700 ns 2.5V V
CC 4.5V, E-temp
1300 ns 2.5V V
CC 5.5V
1300 ns 1.8V V
CC 2.5V (24FC1026)
500 ns 2.5V V
CC 5.5V (24FC1026)
15 TSP Input Filter Spike
Suppression
(SDA and SCL pins)
50 ns All except 24FC1026 (Notes 1 and 3)
16 T
WC Write Cycle Time (byte or
page)
—5ms
17 Endurance 1,000,000 cycles Page mode, 25°C, V
CC = 5.5V (Note 4)
AC CHARACTERISTICS (Continued)
Electrical Characteristics:
Industrial (I): V
CC = +1.7V to 5.5V TA = -40°C to +85°C
Automotive (E): Vcc = +2.5V to 5.5V T
A = -40°C to +125°C
Param.
No.
Sym. Characteristic Min. Max. Units Conditions
Note 1: Not 100% tested. C
B = total capacitance of one bus line in pF.
2: As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region
(minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions.
3: The combined T
SP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved
noise spike suppression. This eliminates the need for a TI specification for standard operation.
4: This parameter is not tested but established by characterization. For endurance estimates in a specific
application, please consult the Total Endurance™ Model which can be obtained from Microchip’s website
at www.microchip.com.
2011-2015 Microchip Technology Inc. DS20002270E-page 5
24AA1026/24LC1026/24FC1026
FIGURE 1-1: BUS TIMING DATA
(unprotected)
(protected)
SCL
SDA
IN
SDA
OUT
WP
5
7
6
15
3
2
89
13
D3
4
10
11
12
14
24AA1026/24LC1026/24FC1026
DS20002270E-page 6 2011-2015 Microchip Technology Inc.
2.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 2-1.
TABLE 2-1: PIN FUNCTION TABLE
2.1 A1, A2 Chip Address Inputs
The A1 and A2 inputs are used by the 24XX1026 for
multiple device operations. The levels on these inputs
are compared with the corresponding bits in the slave
address. The chip is selected if the comparison is true.
Up to four devices may be connected to the same bus
by using different Chip Select bit combinations. In most
applications, the chip address inputs A1 and A2 are
hard-wired to logic ‘0’ or logic ‘1’. For applications in
which these pins are controlled by a microcontroller or
other programmable device, the chip address pins
must be driven to logic ‘0’ or logic ‘1’ before normal
device operation can proceed.
2.2 Serial Data (SDA)
This is a bidirectional pin used to transfer addresses
and data into and data out of the device. It is an
open-drain terminal, therefore, the SDA bus requires a
pull-up resistor to V
CC (typical 10 k for 100 kHz, 2 k
for 400 kHz and 1 MHz).
For normal data transfer, SDA is allowed to change
only during SCL low. Changes during SCL high are
reserved for indicating the Start and Stop conditions.
2.3 Serial Clock (SCL)
This input is used to synchronize the data transfer from
and to the device.
2.4 Write-Protect (WP)
This pin must be connected to either VSS or VCC. If tied
to V
SS, write operations are enabled. If tied to VCC,
write operations are inhibited, but read operations are
not affected.
3.0 FUNCTIONAL DESCRIPTION
The 24XX1026 supports a bidirectional 2-wire bus and
data transmission protocol. A device that sends data
onto the bus is defined as a transmitter and a device
receiving data as a receiver. The bus must be
controlled by a master device which generates the
Serial Clock (SCL), controls the bus access, and
generates the Start and Stop conditions while the
24XX1026 works as a slave. Both master and slave
can operate as a transmitter or receiver, but the master
device determines which mode is activated.
Name PDIP SOIC SOIJ Function
NC 1 1 1 Not Connected
A1 2 2 2 User Configurable Chip Select
A2 3 3 3 User Configurable Chip Select
V
SS 44 4Ground
SDA 5 5 5 Serial Data
SCL 6 6 6 Serial Clock
WP 7 7 7 Write-Protect Input
V
CC 8 8 8 +1.7 to 5.5V (24AA1026)
+2.5 to 5.5V (24LC1026)
+1.8 to 5.5V (24FC1026)

24FC1026T-I/SN

Mfr. #:
Manufacturer:
Microchip Technology
Description:
EEPROM 1024K 128K X 8 2.5V HI-SPD EE 128B PAGE
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union