XC4VLX60-10FF1148I

Virtex-4 Family Overview
DS112 (v3.1) August 30, 2010 www.xilinx.com
Product Specification 7
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Application Notes and Reference Designs
Application notes and reference designs written specifically for the Virtex-4 family are available on the Xilinx web site at
http://www.xilinx.com/support/documentation/virtex-4.htm.
Virtex-4 Device and Package Combinations and Maximum I/Os
Virtex-4 FPGA Ordering Information
Virtex-4 FPGA ordering information shown in Figure 1 applies to all packages including Pb-Free.
Table 2: Virtex-4 Device and Package Combinations and Maximum Available I/Os
Package
(1,2)
SF363
SFG363
FF668
FFG668
FF672
FFG672
FF676
FFG676
FF1148
FFG1148
FF1152
FFG1152
FF1513
FFG1513
FF1517
FFG1517
Size 17x17 27x27 27x27 27x27 35x35 35x35 40x40 40x40
Device MGTs I/O MGTs I/O MGTs I/O MGTs I/O MGTs I/O MGTs I/O MGTs I/O MGTs I/O
XC4VLX15 N/A 240 N/A 320
N/A 320
XC4VLX25 N/A 240 N/A 448
XC4VLX40 N/A 448 N/A 640
XC4VLX60 N/A 448 N/A 640
XC4VLX80 N/A 768
XC4VLX100 N/A 768 N/A 960
XC4VLX160 N/A 768 N/A 960
XC4VLX200 N/A 960
XC4VSX25 N/A 320
XC4VSX35 N/A 448
XC4VSX55 N/A 640
XC4VFX12 N/A 240 N/A 320
XC4VFX20 8320
XC4VFX40 12 352 12 448
XC4VFX60 12 352 16 576
XC4VFX100 20 576 20 768
XC4VFX140
24 768
Notes:
1. All packages are also available in Pb-Free versions (SFG/FFG).
2. Pinouts on all packages (except SF363/SFG363 and FF668/FFG668) are configured using the new, improved SparseChevron pin
layout for superior signal integrity.
Figure 1: Virtex-4 FPGA Ordering Information
Example: XC4VLX25-10FFG668CS2
Device Type
Temperature Range:
C = Commercial (T
J
= 0°C to +8C)
I = Industrial
(2)
(T
J
= –40°C to +100°C)
Number of Pins
Step Identification Version
(1)
Package Type
Speed Grade
(-10, -11, -12
(2)
)
Pb-Free
DS112_01_112806
Notes:
1) The step identification version is optional and is not specified unless
a particular device stepping is required. Refer to the Virtex-4 Data
Sheet (DS302) for additional information on step ordering codes.
2) -12 devices not available in Industrial grade.
Virtex-4 Family Overview
DS112 (v3.1) August 30, 2010 www.xilinx.com
Product Specification 8
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Virtex-4 Documentation
Complete and up-to-date documentation of the Virtex-4
family of FPGAs is available on the Xilinx web site. In addi-
tion to the most recent Virtex-4 Family Overview, the follow-
ing files are also available for download:
Virtex-4 FPGA Data Sheet: DC and Switching
Characteristics
This data sheet contains the DC and Switching Characteris-
tic specifications for the Virtex-4 family.
Virtex-4 FPGA User Guide
This guide includes chapters on:
Clocking Resources
Digital Clock Manager (DCM)
Phase-Matched Clock Dividers (PMCD)
Block RAM and FIFO memory
Configurable Logic Blocks (CLBs)
SelectIO Resources
SelectIO Logic Resources
Advanced SelectIO Logic Resources
XtremeDSP for Virtex-4 FPGAs User Guide
This guide describes the DSP48 slice and includes refer-
ence designs for using DSP48 math functions and various
FIR filters.
Virtex-4 FPGA Configuration Guide
This all-encompassing configuration guide includes chap-
ters on configuration interfaces (serial and SelectMAP), bit-
stream encryption, Boundary-Scan and JTAG configuration,
and reconfiguration techniques.
Virtex-4 FPGA Packaging and Pinout Specification
This specification includes the tables for device/package
combinations and maximum I/Os, pin definitions, pinout
tables, pinout diagrams, mechanical drawings, and thermal
specifications.
Virtex-4 FPGA PCB Designer’s Guide
This guide describes PCB guidelines for the Virtex-4 family.
It covers SelectIO signaling, RocketIO signaling, power dis-
tribution systems, PCB breakout, and parts placement.
Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide
This guide describes the RocketIO Multi-Gigabit Transceiv-
ers available in the Virtex-4 FX family.
Virtex-4 FPGA Embedded Tri-Mode Ethernet MAC User
Guide
This guide describes the Embedded Tri-Mode Ethernet
Media Access Controller available in the Virtex-4 FX family.
PowerPC 405 Processor Block Reference Guide
This guide is updated to include the PowerPC 405 proces-
sor block available in the Virtex-4 FX family.
Revision History
The following table shows the revision history for this document.
Date Version Revision
08/02/04 1.0 Initial Xilinx release. Printed Handbook version.
09/10/04 1.1 Typographical edits.
12/08/04 1.2 Removed System Monitor and ADC references.
Edited Ethernet MAC section.
03/26/05 1.3 Removed legacy CLB reference and typographical edits.
Edited serial transceiver sections.
•In Table 2 added FFG Pb-Free packages.
06/17/05 1.4 Added note to Ta bl e 2 for SparseChevron pinouts.
02/10/06 1.5 Removed FCRAM-II support.
Added note 3 to Ta bl e 1 .
Revised the CLB numbers for XC4VFX40 devices in Table 1 .
Added stepping to order information example in Figure 1.
10/10/06 1.6 Changed maximum transceiver rate to 6.5 Gb/s.
Removed FF1760 package from Ta ble 2 .
01/23/07 2.0 Revision number jumped to 2.0 to correlate to data sheet (DS302) major revision.
Table 1 : Corrected typo: XC4VFX40 number of slices = 18,624.
Table 2 : Added column for FF676 package. Rewrote table footnotes.
Virtex-4 Family Overview
DS112 (v3.1) August 30, 2010 www.xilinx.com
Product Specification 9
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03/12/07 2.1 Ta bl e 2 : Corrected to remove FF676 package offerings in XC4VLX40, XC4VLX60,
XC4VSX25, XC4VSX35, and XC4VFX12 devices.
09/28/07 3.0 All Virtex-4 devices released to Production status. See DS302
, Virtex-4 Data Sheet, for full
particulars. No changes in this document from previous revision.
08/30/10 3.1 See
XCN09028, Product Discontinuation Notice Virtex-4 LX25 FPGA FF(G)676 Devices for
detailed product revisions. In Table 2 , removed XC4VLX25 devices in the FF676/FFG676
package column.
Date Version Revision

XC4VLX60-10FF1148I

Mfr. #:
Manufacturer:
Xilinx
Description:
FPGA - Field Programmable Gate Array
Lifecycle:
New from this manufacturer.
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