
Interface Connectors
The host interface connector conforms to the PCIe Electromechanical Specification.
A mechanical indent is used to separate the PCIe power pins from the differential signal
contacts. The pins are numbered below in ascending order from left to right. Side B re-
fers to component side. Side A refers to the solder side.
AIC HHHL Pin Assignments
The host interface connector conforms to the PCIe Electromechanical Specification.
A mechanical indent is used to separate the PCIe power pins from the differential signal
contacts. The pins are numbered below in ascending order from left to right. Side B re-
fers to component side. Side A refers to the solder side.
Table 13: PCIe Interface Connector Pin Assignments (HHHL Form Factor)
Pin
Number
Side B Side A
Name Description Name Description
1 +12V 12V power PRSNT1# Hot Plug Presence Detect
2 +12V 12V power +12V 12V power
3 +12V 12V power +12V 12V power
4 GND Ground GND Ground
5 SMCLK SMBus clock JTAG2 DNU
6 SMDAT SMBus data JTAG3 DNU
7 GND Ground / UART_HOST JTAG4 DNU
8 +3.3V 3.3V power JTAG5 DNU
9 JTAG1 DNU +3.3V 3.3V power
10 3.3Vaux 3.3V auxiliary power +3.3V 3.3V power
11 WAKE# DNU PERST# PCIe Fundamental Reset
Mechanical Key
12 RSVD Reserved GND Ground
13 GND Ground REFCLK+ PCIe REFCLK p
14 PETp0 PCIe TX Lane 0 p REFCLK- PCIe REFCLK n
15 PETn0 PCIe TX Lane 0 n GND Ground
16 GND Ground PERp0 PCIe RX Lane 0 p
17 PRSNT2# DNU PERn0 PCIe RX Lane 0 n
18 GND Ground GND Ground
19 PETp1 PCIe TX Lane 1 p RSVD Reserved
20 PETn1 PCIe TX Lane 1 n GND Ground
21 GND Ground PERp1 PCIe RX Lane 1 p
22 GND Ground PERn1 PCIe RX Lane 1 n
23 PETp2 PCIe TX Lane 2 p GND Ground
24 PETn2 PCIe TX Lane 2 n GND Ground
25 GND Ground PERp2 PCIe RX Lane 2 p
9100 U.2 and HHHL NVMe PCIe SSDs
Interface Connectors
CCMTD-731836775-1
9100_hhhl_u2_nvme_pcie_ssd.pdf - Rev. I 03/17 EN
16
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