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SST39VF010-70-4I-WHE

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28
©2012 Silicon Storage Technology, Inc. DS25023B 06/13
16
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF010 / SST39LF020 / SST39LF040
SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Figure 8: Toggle Bit Timing Diagram
Figure 9: WE# Controlled Sector-Erase Timing Diagram
1150 F07.0
ADDRESS A
MS-0
DQ
6
WE#
OE#
CE#
T
OE
T
OEH
T
CE
T
OES
TWO READ CYCLES
WITH SAME OUTPUTS
Note: A
MS
= Most significant address
A
MS
= A
16
for SST39LF/VF010, A
17
for SST39LF/VF020 and A
18
for SST39LF/VF040
1150 F08.0
ADDRESS A
MS-0
DQ
7-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
5555 2AAA 2AAA5555 5555
55 3055AA 80 AA
SA
X
OE#
CE#
SIX-BYTE CODE FOR SECTOR-ERASE
T
SE
T
WP
Note: This device also supports CE# controlled Sector-Erase operation. The WE# and CE# signals are
interchageable as long as minmum timings are met. (See Table 10)
SA
X
= Sector Address
A
MS
= Most significant address
A
MS
= A
16
for SST39LF/VF010, A
17
for SST39LF/VF020, and A
18
for SST39LF/VF040
©2012 Silicon Storage Technology, Inc. DS25023B 06/13
17
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF010 / SST39LF020 / SST39LF040
SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Figure 10:WE# Controlled Chip-Erase Timing Diagram
Figure 11:Software ID Entry and Read
1150 F17.0
ADDRESS A
MS-0
DQ
7-0
WE#
SW0 SW1 SW2 SW3 SW4 SW5
5555 2AAA 2AAA5555 5555
55 1055AA 80 AA
5555
OE#
CE#
SIX-BYTE CODE FOR CHIP-ERASE
T
SCE
T
WP
Note: This device also supports CE# controlled Chip-Erase operation. The WE# and CE# signals are
interchageable as long as minmum timings are met. (See Table 10)
A
MS
= Most significant address
A
MS
= A
16
for SST39LF/VF010, A
17
for SST39LF/VF020, and A
18
for SST39LF/VF040
1150 F09.2
Note: Device ID = D5H for SST39LF/VF010, D6H for SST39LF/VF020, and D7H for SST39LF/VF040.
ADDRESS A
14-0
T
IDA
DQ
7-0
WE#
SW0 SW1 SW2
5555 2AAA 5555 0000 0001
OE#
CE#
Three-byte Sequence for
Software ID Entry
T
WP
T
WPH
T
AA
BF
Device ID
55AA 90
©2012 Silicon Storage Technology, Inc. DS25023B 06/13
18
1 Mbit / 2 Mbit / 4 Mbit Multi-Purpose Flash
SST39LF010 / SST39LF020 / SST39LF040
SST39VF010 / SST39VF020 / SST39VF040
Data Sheet
Figure 12:Software ID Exit and Reset
Figure 13:AC Input/Output Reference Waveforms
Figure 14:A Test Load Example
1150 F10.0
ADDRESS A
14-0
DQ
7-0
T
IDA
T
WP
T
WHP
WE#
SW0 SW1 SW2
5555 2AAA 5555
THREE-BYTE SEQUENCE FOR
SOFTWARE ID EXIT AND RESET
OE#
CE#
AA 55 F0
1150 F12.1
REFERENCE POINTS OUTPUTINPUT
V
IT
V
IHT
V
ILT
V
OT
AC test inputs are driven at V
IHT
(0.9 V
DD
) for a logic “1” and V
ILT
(0.1 V
DD
) for a logic
“0”. Measurement reference points for inputs and outputs are V
IT
(0.5 V
DD
) and V
OT
(0.5 V
DD
). Input
rise and fall times (10%
↔ 90%) are <5 ns.
Note: V
IT
- V
INPUT
Test
V
OT
- V
OUTPUT
Test
V
IHT
- V
INPUT
HIGH Test
V
ILT
- V
INPUT
LOW Test
1150 F11.1
TO TESTER
TO DUT
C
L
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P28

SST39VF010-70-4I-WHE

Mfr. #:
Buy SST39VF010-70-4I-WHE
Manufacturer:
Microchip Technology
Description:
NOR Flash 128K X 8 70ns
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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