AD7730/AD7730L
–34–
POWER SUPPLIES
There is no specific power sequence required for the AD7730,
either the AV
DD
or the DV
DD
supply can come up first. While
the latch-up performance of the AD7730 is very good, it is
important that power is applied to the AD7730 before signals at
REF IN, AIN or the logic input pins in order to avoid latch-up
caused by excessive current. If this is not possible, the current
that flows in any of these pins should be limited to less than 30
mA per pin and less than 100 mA cumulative. If separate sup-
plies are used for the AD7730 and the system digital circuitry,
the AD7730 should be powered up first. If it is not possible to
guarantee this, current limiting resistors should be placed in
series with the logic inputs to again limit the current to less than
30 mA per pin and less than 100 mA total.
Grounding and Layout
Since the analog inputs and reference input are differential,
most of the voltages in the analog modulator are common-mode
voltages. The excellent common-mode rejection of the part will
remove common-mode noise on these inputs. The analog and
digital supplies to the AD7730 are independent and separately
pinned out to minimize coupling between the analog and digital
sections of the device. The digital filter will provide rejection of
broadband noise on the power supplies, except at integer mul-
tiples of the modulator sampling frequency or multiples of the
chop frequency in chop mode. The digital filter also removes
noise from the analog and reference inputs provided those noise
sources do not saturate the analog modulator. As a result, the
AD7730 is more immune to noise interference than a conven-
tional high resolution converter. However, because the resolu-
tion of the AD7730 is so high and the noise levels from the
AD7730 so low, care must be taken with regard to grounding
and layout.
The printed circuit board that houses the AD7730 should be
designed so the analog and digital sections are separated and
confined to certain areas of the board. This facilitates the use of
ground planes that can be easily separated. A minimum etch
technique is generally best for ground planes as it gives the best
shielding. Digital and analog ground planes should only be
joined in one place. If the AD7730 is the only device requiring
an AGND to DGND connection, the ground planes should
be connected at the AGND and DGND pins of the AD7730. If
the AD7730 is in a system where multiple devices require AGND
to DGND connections, the connection should still be made at
one point only, a star ground point that should be established as
closely as possible to the AD7730.
Avoid running digital lines under the device as these will couple
noise onto the die. The analog ground plane should be allowed
to run under the AD7730 to avoid noise coupling. The power
supply lines to the AD7730 should use as large a trace as pos-
sible to provide low impedance paths and reduce the effects of
glitches on the power supply line. Fast switching signals such as
clocks should be shielded with digital ground to avoid radiating
noise to other sections of the board and clock signals should
never be run near the analog inputs. Avoid crossover of digital
and analog signals. Traces on opposite sides of the board should
run at right angles to each other. This will reduce the effects of
feedthrough through the board. A microstrip technique is by far
the best but is not always possible with a double-sided board. In
this technique, the component side of the board is dedicated to
ground planes while signals are placed on the solder side.
Good decoupling is important when using high resolution
ADCs. All analog supplies should be decoupled with 10 μF
tantalum in parallel with 0.1 μF ceramic capacitors to AGND.
To achieve the best from these decoupling components, they
have to be placed as close as possible to the device, ideally right
up against the device. All logic chips should be decoupled with
0.1 μF disc ceramic capacitors to DGND. In systems where a
common supply voltage is used to drive both the AV
DD
and
DV
DD
of the AD7730, it is recommended that the system’s
AV
DD
supply is used. This supply should have the recom-
mended analog supply decoupling capacitors between the AV
DD
pin of the AD7730 and AGND and the recommended digital
supply decoupling capacitor between the DV
DD
pin of the
AD7730 and DGND.
Evaluating the AD7730 Performance
A recommended layout for the AD7730 is outlined in the evalu-
ation board for the AD7730. The evaluation board package
includes a fully assembled and tested evaluation board, docu-
mentation, software for controlling the board over the printer
port of a PC and software for analyzing the AD7730’s perfor-
mance on the PC. The evaluation board order number is
EVAL-AD7730EB.
Noise levels in the signals applied to the AD7730 may also
affect performance of the part. The AD7730 allows two tech-
niques for evaluating the true performance of the part, indepen-
dent of the analog input signal. These schemes should be used
after a calibration has been performed on the part.
The first method is to select the AIN1(–)/AIN1(–) input chan-
nel arrangement. In this case, the differential inputs to the
AD7730 are internally shorted together to provide a zero differ-
ential voltage for the analog modulator. External to the device,
the AIN1(–) input should be connected to a voltage which is
within the allowable common-mode range of the part.
The second scheme is to evaluate the part with a voltage near
input full scale. This can be achieved by again using input pair
AIN1(–), but by adding a differential voltage via the TARE
DAC. This allows the user to evaluate noise performance with a
near full-scale voltage.
The software in the evaluation board package allows the user to
look at the noise performance in terms of counts, bits and nV.
Once the user has established that the noise performance of the
part is satisfactory in this mode, an external input voltage can
then be applied to the device incorporating more of the signal
chain.
REV. B
AD7730/AD7730L
–35–
SERIAL INTERFACE
The AD7730’s programmable functions are controlled via a set
of on-chip registers. Access to these registers is via the part’s
serial interface. After power-on or RESET, the device expects a
write to its Communications Register. The data written to this
register determines whether the next operation to the part is a
read or a write operation and also determines to which register
this read or write operation occurs. Therefore, write access to
one of the control registers on the part starts with a write opera-
tion to the Communications Register followed by a write to the
selected register. Reading from the part’s on-chip registers can
take the form of either a single or continuous read. A single read
from a register consists of a write to the Communications Regis-
ter (with RW1 = 0 and RW0 = 1) followed by the read from the
specified register. To perform continuous reads from a register,
write to the Communications Register (with RW1 = 1 and
RW0 = 0) to place the part in continuous read mode. The speci-
fied register can then be read from continuously until a write
operation to the Communications Register (with RW1 = 1 and
RW0 = 1) which takes the part out of continuous read mode.
When operating in continuous read mode, the part is continu-
ously monitoring its DIN line. The DIN line should therefore
be permanently low to allow the part to stay in continuous read
mode. Figure 5 and Figure 6, shown previously, indicate the
correct flow diagrams when reading and writing from the
AD7730’s registers.
The AD7730’s serial interface consists of five signals, CS,
SCLK, DIN, DOUT and RDY. The DIN line is used for
transferring data into the on-chip registers while the DOUT line
is used for accessing data from the on-chip registers. SCLK is
the serial clock input for the device and all data transfers (either
on DIN or DOUT) take place with respect to this SCLK signal.
Write Operation
The transfer of data into the part is to an input shift register. On
completion of a write operation, data is transferred to the speci-
fied register. This internal transfer will not take place until the
correct number of bits for the specified register have been
loaded to the input shift register. For example, the transfer of
data from the input shift register takes place after eight serial
clock cycles for a DAC Register write, while the transfer of data
from the input shift register takes place after 24 serial clock
cycles when writing to the Filter Register. Figure 18 shows a
timing diagram for a write operation to the input shift register of
the AD7730. With the POL input at a logic high, the data is
latched into the input shift register on the rising edge of SCLK.
With the POL input at a logic low, the data is latched into the
input shift register on the falling edge of SCLK.
Figure 18 also shows the CS input being used to decode the
write operation to the AD7730. However, this CS input can be
used in a number of different ways. It is possible to operate the
part in three-wire mode where the CS input is tied low perma-
nently. In this case, the SCLK line should idle high between
data transfer when the POL input is high and should idle low
between data transfers when the POL input is low. For POL = 1,
the first falling edge of SCLK clocks data from the microcontrol-
ler onto the DIN line of the AD7730. It is then clocked into the
input shift register on the next rising edge of SCLK. For POL = 0,
the first clock edge that clocks data from the microcontroller
onto the DIN line of the AD7730 is a rising edge. It is then
clocked into the input shift register on the next falling edge of
SCLK.
In other microcontroller applications which require a decoding
of the AD7730, CS can be generated from a port line. In this
case, CS would go low well in advance of the first falling edge of
SCLK (POL = 1) or the first rising edge of SCLK (POL = 0).
Clocking of each bit of data is as just described.
In DSP applications, the SCLK is generally a continuous clock.
In these applications, the CS input for the AD7730 is generated
from a frame synchronization signal from the DSP. For proces-
sors with the rising edge of SCLK as the active edge, the POL
input should be tied high. For processors with the falling edge of
SCLK as the active edge, the POL input should be tied low. In
these applications, the first edge after CS goes low is the active
edge. The MSB of the data to be shifted into the AD7730 must
be set up prior to this first active edge.
Read Operation
The reading of data from the part is from an output shift regis-
ter. On initiation of a read operation, data is transferred from
the specified register to the output shift register. This is a paral-
lel shift and is transparent to the user. Figure 19 shows a timing
diagram for a read operation from the output shift register of the
AD7730. With the POL input at a logic high, the data is clocked
out of the output shift register on the falling edge of SCLK.
With the POL input at a logic low, the data is clocked out of the
output shift register on the rising edge of SCLK.
Figure 19 also shows the CS input being used to decode the
read operation to the AD7730. However, this CS input can be
used in a number of different ways. It is possible to operate the
part in three-wire mode where the CS input is permanently tied
low. In this case, the SCLK line should idle high between data
transfer when the POL input is high, and should idle low be-
tween data transfers when the POL input is low. For POL = 1,
the first falling edge of SCLK clocks data from the output shift
register onto the DOUT line of the AD7730. It is then clocked
into the microcontroller on the next rising edge of SCLK. For
POL = 0, the first clock edge that clocks data from the AD7730
onto the DOUT line is a rising edge. It is then clocked into the
microcontroller on the next falling edge of SCLK.
In other microcontroller applications which require a decoding
of the AD7730, CS can be generated from a port line. In this
case, CS would go low well in advance of the first falling edge of
SCLK (POL = 1) or the first rising edge of SCLK (POL = 0).
Clocking of each bit of data is as just described.
REV. B
AD7730/AD7730L
–36–
In DSP applications, the SCLK is generally a continuous clock.
In these applications, the CS input for the AD7730 is generated
from a frame synchronization signal from the DSP. In these
applications, the first edge after CS goes low is the active edge.
The MSB of the data to be shifted into the DSP must be set up
prior to this first active edge. Unlike microcontroller applica-
tions, the DSP does not provide a clock edge to clock the MSB
from the AD7730. In this case, the CS of the AD7730 places
the MSB on the DOUT line. For processors with the rising edge
of SCLK as the active edge, the POL input should be tied high.
In this case, the DSP takes data on the rising edge. If CS goes
low while SCLK is low, the MSB is clocked out on the DOUT
line from the CS. Subsequent data bits are clocked from the
falling edge of SCLK. For processors with the falling edge of
SCLK as the active edge, the POL input should be tied low. In
this case, the DSP takes data on the falling edge. If CS goes low
while SCLK is high, the MSB is clocked out on the DOUT line
from the CS. Subsequent data bits are clocked from the rising
edge of SCLK.
Figure 18. Read Cycle Timing Diagram
Figure 19. Write Cycle Timing Diagram
The RDY line is used as a status signal to indicate when data is
ready to be read from the AD7730’s data register. RDY goes
low when a new data word is available in the data register. It is
reset high when a read operation from the data register is com-
plete. It also goes high prior to the updating of the data register
to indicate when a read from the data register should not be
initiated. This is to ensure that the transfer of data from the data
register to the output shift register does not occur while the data
register is being updated. It is possible to read the same data
twice from the output register even though the RDY line returns
high after the first read operation. Care must be taken, however,
to ensure that the read operations are not initiated as the next
output update is about to take place.
For systems with a single data line, the DIN and DOUT lines
on the AD7730 can be connected together, but care must be
taken in this case not to place the part in continuous read mode
as the part monitors DIN while supplying data on DOUT and
as a result, it may not be possible to take the part out of its
continuous read mode.
DOUT
SCLK
(POL = 1)
CS
RDY
MSB
t
5
t
7
t
9
LSB
t
8
t
6
t
4
t
3
t
10
SCLK
(POL = 0)
t
5A
t
6
t
7
DIN
SCLK
(POL = 1)
CS
MSB
t
12
t
15
LSB
t
16
t
14
t
11
t
13
SCLK
(POL = 0)
t
14
t
15
REV. B

AD7730LBRZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog to Digital Converters - ADC CMOS 24-Bit Low Pwr
Lifecycle:
New from this manufacturer.
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