MT9HVF6472PKZ-667G1 Datasheet MT9HVF12872PKZ-80EH1, MT9HVF6472PKZ-667G1 | P13-P15

Table 11: I

DD

Specifications and Conditions – 1GB (Die Revision M)

Values shown for MT47H128M8 DDR2 SDRAM only and are computed from values specified in the 1Gb (128 Meg x 8) com-

ponent data sheet

Parameter/Condition Symbol

-80E

-800 -667 Units

Operating one bank active-precharge current:

t

CK =

t

CK (I

DD

),

t

RC =

t

RC (I

DD

),

t

RAS =

t

RAS MIN (I

DD

); CKE is HIGH, S# is HIGH between valid commands; Address

bus inputs are switching; Data bus inputs are switching

I

DD0

585 540 mA

Operating one bank active-read-precharge current: I

OUT

= 0mA; BL = 4, CL = CL

(I

DD

), AL = 0;

t

CK =

t

CK (I

DD

),

t

RC =

t

RC (I

DD

),

t

RAS =

t

RAS MIN (I

DD

),

t

RCD =

t

RCD (I

DD

);

CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;

Data pattern is same as I

DD4W

I

DD1

675 630 mA

Precharge power-down current: All device banks idle;

t

CK =

t

CK (I

DD

); CKE is LOW;

Other control and address bus inputs are stable; Data bus inputs are floating

I

DD2P

90 90 mA

Precharge quiet standby current: All device banks idle;

t

CK =

t

CK (I

DD

); CKE is

HIGH, S# is HIGH; Other control and address bus inputs are stable; Data bus inputs

are floating

I

DD2Q

216 216 mA

Precharge standby current: All device banks idle;

t

CK =

t

CK (I

DD

); CKE is HIGH, S#

is HIGH; Other control and address bus inputs are switching; Data bus inputs are

switching

I

DD2N

252 216 mA

Active power-down current: All device banks open;

t

CK =

t

CK

(I

DD

); CKE is LOW; Other control and address bus inputs are stable;

Data bus inputs are floating

Fast PDN exit

MR[12] = 0

I

DD3P

270 252 mA

Slow PDN exit

MR[12] = 1

180 180 mA

Active standby current: All device banks open;

t

CK =

t

CK (I

DD

),

t

RAS =

t

RAS MAX

(I

DD

),

t

RP =

t

RP (I

DD

); CKE is HIGH, S# is HIGH between valid commands; Other control

and address bus inputs are switching; Data bus inputs are switching

I

DD3N

297 270 mA

Operating burst write current: All device banks open; Continuous burst writes;

BL = 4, CL = CL (I

DD

), AL = 0;

t

CK =

t

CK (I

DD

),

t

RAS =

t

RAS MAX (I

DD

),

t

RP =

t

RP (I

DD

);

CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are switching;

Data bus inputs are switching

I

DD4W

1125 1035 mA

Operating burst read current: All device banks open; Continuous burst reads; I

OUT

= 0mA; BL = 4, CL = CL (I

DD

), AL = 0;

t

CK =

t

CK (I

DD

),

t

RAS =

t

RAS MAX (I

DD

),

t

RP =

t

RP

(I

DD

); CKE is HIGH, S# is HIGH between valid commands; Address bus inputs are

switching; Data bus inputs are switching

I

DD4R

1080 990 mA

Burst refresh current:

t

CK =

t

CK (I

DD

); REFRESH command at every

t

RFC (I

DD

) inter-

val; CKE is HIGH, S# is HIGH between valid commands; Other control and address bus

inputs are switching; Data bus inputs are switching

I

DD5

1395 1350 mA

Self refresh current: CK and CK# at 0V; CKE ≤ 0.2V; Other control and address bus

inputs are floating; Data bus inputs are floating

I

DD6

63 63 mA

Operating bank interleave read current: All device banks interleaving reads;

I

OUT

= 0mA; BL = 4, CL = CL (I

DD

), AL =

t

RCD (I

DD

) - 1 ×

t

CK (I

DD

);

t

CK =

t

CK (I

DD

),

t

RC =

t

RC (I

DD

),

t

RRD =

t

RRD (I

DD

),

t

RCD =

t

RCD (I

DD

); CKE is HIGH, S# is HIGH between valid

commands; Address bus inputs are stable during deselects; Data bus inputs are

switching

I

DD7

1890 1665 mA

512MB, 1GB (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM

IDD Specifications

PDF: 09005aef83d09b45

hvf9c64_128x72pkz.pdf - Rev. C 4/14 EN

13

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Register and PLL Specifications

Table 12: Register Specifications

SSTU32866 devices or equivalent

Parameter Symbol Pins Condition Min Max Units

DC high-level

input voltage

V

IH(DC)

Control, command,

address

SSTL_18 V

REF(DC)

+ 125 V

DDQ

+ 250 mV

DC low-level

input voltage

V

IL(DC)

Control, command,

address

SSTL_18 0 V

REF(DC)

- 125 mV

AC high-level

input voltage

V

IH(AC)

Control, command,

address

SSTL_18 V

REF(DC)

+ 250 – mV

AC low-level

input voltage

V

IL(AC)

Control, command,

address

SSTL_18 – V

REF(DC)

- 250 mV

Output high

voltage

V

OH

Parity output LVCMOS 1.2 – V

Output low voltage V

OL

Parity output LVCMOS – 0.5 V

Input current I

I

All pins V

I

= V

DD

or V

SS

– ±0.5 µA

Static standby I

DD

All pins RESET# = V

SSQ

(I

O

= 0) – 100 µA

Static operating I

DD

All pins RESET# = V

SS

; V

I

= V

IH(AC)

or V

IL(DC)

I

O

= 0

– 40 mA

Dynamic operating

(clock tree)

I

DDD

N/A RESET# = V

DD

;

V

I

= V

IH(DC)

or V

IL(AC)

,

I

O

= 0; CK and CK#

switching 50% duty cy-

cle

– Varies by

manufacturer

µA

Dynamic operating

(per each input)

I

DDD

N/A RESET# = V

DD

;

V

I

= V

IH(AC)

or V

IL(DC)

,

I

O

= 0; CK and CK#

switching 50% duty

cycle; One data in/out

switching at

t

CK/2,

50% duty cycle

– Varies by

manufacturer

µA

Input capacitance

(per device, per pin)

C

IN

All inputs except

RESET#

V

I

= V

REF

±250mV;

V

DD

= 1.8V

2.5 3.5 pF

Input capacitance

(per device, per pin)

C

IN

RESET# V

I

= V

DD

or V

SS

Varies by

manufacturer

Varies by

manufacturer

pF

Note:

1. Timing and switching specifications for the register listed are critical for proper opera-

tion of the DDR2 SDRAM RDIMMs. These are meant to be a subset of the parameters for

the specific device used on the module. Detailed information for this register is available

in JEDEC standard JESD82.

512MB, 1GB (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM

Register and PLL Specifications

PDF: 09005aef83d09b45

hvf9c64_128x72pkz.pdf - Rev. C 4/14 EN

14

Micron Technology, Inc. reserves the right to change products or specifications without notice.

Table 13: PLL Specifications

CU877 device or equivalent

Parameter Symbol Pins Condition Min Max Units

DC high-level

input voltage

V

IH

RESET# LVCMOS 0.65 × V

DD

– V

DC low-level

input voltage

V

IL

RESET# LVCMOS – 0.35 × V

DD

V

Input voltage (limits) V

IN

RESET#, CK,

CK#

– - 0.3 V

DD

+ 0.3 V

DC high-level

input voltage

V

IH

CK, CK# Differential input 0.65 × V

DD

– V

DC low-level

input voltage

V

IL

CK, CK# Differential input – 0.35 × V

DD

V

Input differential-pair

cross voltage

V

IX

CK, CK# Differential input (V

DDQ

/2) - 0.15 (V

DD

/2) + 0.15 V

Input differential

voltage

V

ID(DC)

CK, CK# Differential input 0.3 V

DD

+ 0.4 V

Input differential

voltage

V

ID(AC)

CK, CK# Differential input 0.6 V

DD

+ 0.4 V

Input current I

I

RESET# V

I

= V

DD

or V

SS

–10 10 µA

CK, CK# V

I

= V

DD

or V

SS

–250 250 µA

Output disabled

current

I

ODL

RESET# = V

SS

; V

I

= V

IH(AC)

or V

IL(DC)

100 – µA

Static supply current I

DDLD

CK = CK# = LOW – 500 µA

Dynamic supply I

DD

N/A CK, CK# = 270 MHz, all

outputs open (not con-

nected to PCB)

– 300 mA

Input capacitance C

IN

Each input V

I

= V

DD

or V

SS

2 3 pF

Table 14: PLL Clock Driver Timing Requirements and Switching Characteristics

Parameter Symbol Min Max Units

Stabilization time

t

L – 15 μs

Input clock slew rate slr(i) 1.0 4.0 V/ns

SSC modulation frequency – 30 33 kHz

SSC clock input frequency deviation – 0.0 –0.5 %

PLL loop bandwidth (–3dB from unity gain) – 2.0 – MHz

Note:

1. PLL timing and switching specifications are critical for proper operation of the DDR2

DIMM. This is a subset of parameters for the specific PLL used. Detailed PLL information

is available in JEDEC standard JESD82.

512MB, 1GB (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM

Register and PLL Specifications

PDF: 09005aef83d09b45

hvf9c64_128x72pkz.pdf - Rev. C 4/14 EN

15

Micron Technology, Inc. reserves the right to change products or specifications without notice.

MT9HVF6472PKZ-667G1

MT9HVF6472PKZ-667G1

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