Serial Presence-Detect
For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.
Table 15: SPD EEPROM Operating Conditions
Parameter/Condition Symbol Min Max Units
Supply voltage V
DDSPD
1.7 3.6 V
Input high voltage: logic 1; All inputs V
IH
V
DDSPD
× 0.7 V
DDSPD
+ 0.5 V
Input low voltage: logic 0; All inputs V
IL
–0.6 V
DDSPD
× 0.3 V
Output low voltage: I
OUT
= 3mA V
OL
0.4 V
Input leakage current: V
IN
= GND to V
DD
I
LI
0.1 3 µA
Output leakage current: V
OUT
= GND to V
DD
I
LO
0.05 3 µA
Standby current I
SB
1.6 4 µA
Power supply current, READ: SCL clock frequency = 100 kHz I
CCR
0.4 1 mA
Power supply current, WRITE: SCL clock frequency = 100 kHz I
CCW
2 3 mA
Table 16: SPD EEPROM AC Operating Conditions
Parameter/Condition Symbol Min Max Units Notes
SCL LOW to SDA data-out valid
t
AA 0.2 0.9 µs 1
Time bus must be free before a new transition can start
t
BUF 1.3 µs
Data-out hold time
t
DH 200 ns
SDA and SCL fall time
t
F 300 ns 2
SDA and SCL rise time
t
R 300 ns 2
Data-in hold time
t
HD:DAT 0 µs
Start condition hold time
t
HD:STA 0.6 µs
Clock HIGH period
t
HIGH 0.6 µs
Noise suppression time constant at SCL, SDA inputs
t
I 50 ns
Clock LOW period
t
LOW 1.3 µs
SCL clock frequency
t
SCL 400 kHz
Data-in setup time
t
SU:DAT 100 ns
Start condition setup time
t
SU:STA 0.6 µs 3
Stop condition setup time
t
SU:STO 0.6 µs
WRITE cycle time
t
WRC 10 ms 4
Notes:
1. To avoid spurious start and stop conditions, a minimum delay is placed between SCL = 1
and the falling or rising edge of SDA.
2. This parameter is sampled.
3. For a restart condition or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (
t
WRC) is the time from a valid stop condition of a
write sequence to the end of the EEPROM internal ERASE/PROGRAM cycle. During the
WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to
pull-up resistance, and the EEPROM does not respond to its slave address.
512MB, 1GB (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM
Serial Presence-Detect
PDF: 09005aef83d09b45
hvf9c64_128x72pkz.pdf - Rev. C 4/14 EN
16
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
Module Dimensions
Figure 3: 244-Pin DDR2 VLP Mini-RDIMM
82.127 (3.233)
81.873 (3.223)
Front view
18.3 (0.72)
18.1(0.713)
10.0 (0.394)
TYP
1.0 (0.039)
TYP
1.0 (0.039) R
X2
0.5 (0.02) R
1.8 (0.071) D
X2
6.0 (0.236)
TYP
2.0 (0.079)
TYP
78.0 (3.071)
TYP
0.6 (0.024)
TYP
0.45 (0.018)
TYP
Pin 1
Pin 122
42.9 (1.689)
TYP
Back view
3.3 (0.13)
TYP
3.6 (0.142) TYP
33.6 (1.323)
TYP
38.4 (1.512)
TYP
3.2 (0.126)
TYP
3.8 (0.15)
MAX
1.1 (0.043)
0.9 (0.035)
Pin 244
Pin 123
U1 U2 U3
U4
U5
U6 U7
U8 U9
U10
U11
U12
U13
45° X4
Notes:
1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only. Refer to the JEDEC MO document for
complete design dimensions.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
512MB, 1GB (x72, ECC, SR) 244-Pin DDR2 VLP Mini-RDIMM
Module Dimensions
PDF: 09005aef83d09b45
hvf9c64_128x72pkz.pdf - Rev. C 4/14 EN
17
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.

MT9HVF6472PKZ-667G1

Mfr. #:
Manufacturer:
Micron
Description:
DRAM Module DDR2 SDRAM 512Mbyte 244MiniRDIMM
Lifecycle:
New from this manufacturer.
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