© Semiconductor Components Industries, LLC, 2011
September, 2011 − Rev. 5
1 Publication Order Number:
NB4N111K/D
NB4N111K
3.3V Differential In 1:10
Differential Fanout Clock
Driver with HCSL Level
Output
Description
The NB4N111K is a differential input clock 1 to 10 HCSL fanout
buffer, optimized for ultra low propagation delay variation. The
NB4N111K is designed with HCSL clock distribution for FBDIMM
applications in mind.
Inputs can accept differential LVPECL, CML, or LVDS levels.
Single−ended LVPECL, CML, LVCMOS or LVTTL levels are
accepted with the proper V
REFAC
supply (see Figures 5, 10, 11, 12,
and 13). Clock input pins incorporate an internal 50 W on die
termination resistors. Outputs can interface with LVDS with proper
termination (See Figure 15).
The NB4N111K specifically guarantees low output–to–output
skews. Optimal design, layout, and processing minimize skew within
a device and from device to device. System designers can take
advantage of the NB4N111K’s performance to distribute low skew
clocks across the backplane or the motherboard.
Features
• Typical Input Clock Frequencies: 100, 133, 166, 200, 266, 333, and
400 MHz
• 340 ps Typical Rise and Fall Times
• 800 ps Typical Propagation Delay
• Dtpd 100 ps Maximum Propagation Delay Variation Per Each
Differential Pair
• <1 ps RMS Additive Clock jitter
• Operating Range: V
CC
= 3.0 V to 3.6 V with V
EE
= 0 V
• Differential HCSL Output Level or LVDS with Proper Termination
• These are Pb−Free Devices
A = Assembly Site
WL = Wafer Lot
YY = Year
WW = Work Week
G = Pb−Free Package
*For additional marking information, refer to
Application Note AND8002/D.
QFN32
MN SUFFIX
CASE 488AM
MARKING DIAGRAM*
http://onsemi.com
NB4N
111K
AWLYYWWG
1
32
Figure 1. Pin Configuration (Top View)
Q0
Q0
Q1
Q1
Q8
Q8
Q9
Q9
CLK
CLK
V
CC
GND
R
REF
I
REF
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
ORDERING INFORMATION
VTCLK
VTCLK
32
1
