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SN74ABT853PWE4

SN74ABT853PWE4
Mfr. #:
SN74ABT853PWE4
Description:
Bus Transceivers 8 to 9-Bit Parity Bus Transceivers
Lifecycle:
New from this manufacturer.
Datasheet:
SN74ABT853PWE4 Datasheet
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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ECAD Model:
More Information:
SN74ABT853PWE4 more Information SN74ABT853PWE4 Product Details
Product Attribute
Attribute Value
Manufacturer:
Texas Instruments
Product Category:
Bus Transceivers
RoHS:
Y
Logic Family:
74ABT
Input Level:
TTL
Output Level:
TTL
Output Type:
3-State
High Level Output Current:
- 32 mA
Low Level Output Current:
64 mA
Propagation Delay Time:
4.8 ns
Supply Voltage - Max:
5.5 V
Supply Voltage - Min:
4.5 V
Minimum Operating Temperature:
- 40 C
Maximum Operating Temperature:
+ 85 C
Package / Case:
TSSOP-24
Packaging:
Tube
Function:
Bus Transceiver with Parity Checker
Height:
1.15 mm
Length:
7.8 mm
Number of Circuits:
1
Product:
BiCMOS
Quiescent Current:
24 mA
Technology:
BiCMOS
Width:
4.4 mm
Brand:
Texas Instruments
Mounting Style:
SMD/SMT
Number of Channels:
8
Supply Current - Max:
38 mA
Operating Supply Voltage:
4.5 V to 5.5 V
Polarity:
Non-Inverting
Product Type:
Bus Transceivers
Factory Pack Quantity:
1
Subcategory:
Logic ICs
Unit Weight:
0.003175 oz
Tags
SN74ABT853P, SN74ABT853, SN74ABT85, SN74ABT8, SN74AB, SN74A, SN74, SN7
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Step1: Vacuum Packaging with PL
Step1:
Vacuum Packaging with PL
Step2: Anti-Static Bag
Step2:
Anti-Static Bag
Step3: Packaging Boxes
Step3:
Packaging Boxes
***i-Key
IC TRANSCVR 8-9BIT INV 24TSSOP
***as Instruments
The 'ABT853 8-bit to 9-bit parity transceivers are designed for communication between data buses. When data is transmitted from the A bus to the B bus, a parity bit is generated. When data is transmitted from the B bus to the A bus with its corresponding parity bit, the open-collector parity-error (ERR\) output indicates whether or not an error in the B data has occurred. The output-enable (OEA\ and OEB\) inputs can be used to disable the device so that the buses are effectively isolated. The 'ABT853 transceivers provide true data at their outputs. A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports with the ERR\ flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the latch-enable (LE\) and clear (CLR\) control inputs. When both OEA\ and OEB\ are low, data is transferred from the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the designer more system diagnostic capability. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
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Available
On Order:
3500
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