TMS32C5517AZCHA20R

Mfr. #:: TMS32C5517AZCHA20R
Description:: Digital Signal Processors & Controllers - DSP, DSC TMS320C5517 low-power digital signal processor 196-NFBGA -40 to 85
Lifecycle:: New from this manufacturer.
Datasheet:: TMS32C5517AZCHA20R Datasheet
Delivery:: DHL FedEx Ups TNT EMS
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More Information:: TMS32C5517AZCHA20R more Information TMS32C5517AZCHA20R Product Details

Product Attribute
Attribute Value

Manufacturer:: Texas Instruments

Product Category:: Digital Signal Processors & Controllers - DSP, DSC

RoHS:: Y

Mounting Style:: SMD/SMT

Package / Case:: NFBGA-196

Series:: TMS320C5517

Product:: DSPs

Core:: C55x

Maximum Clock Frequency:: 75 MHz

Data RAM Size:: 64 kB, 256 kB

Operating Supply Voltage:: 1.05 V

Minimum Operating Temperature:: - 40 C

Maximum Operating Temperature:: + 85 C

Brand:: Texas Instruments

Data ROM Size:: 128 kB

Interface Type:: I2C, SPI, UART, USB

Data Bus Width:: 8 bit, 16 bit

I/O Voltage:: 1.8 V, 2.75 V, 3.3 V

Instruction Type:: Fixed Point

Moisture Sensitive:: Yes

Product Type:: DSP - Digital Signal Processors & Controllers

Factory Pack Quantity:: 1000

Subcategory:: Embedded Processors & Controllers

Supply Voltage - Max:: 1.15 V

Supply Voltage - Min:: 0.998 V

Watchdog Timers:: Watchdog Timer

Tags: TMS32C5, TMS32C, TMS32, TMS3, TMS

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We provide 90-360 days warranty.

If the items you received were not in perfect quality, we would be responsible for your refund or replacement, but the items must be returned in their original condition.
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Email: info@omo-ic.com

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TMS32C5517AZCHA20R Description

***: This device is a member of TI's C5000 fixed-point Digital Signal Processor (DSP) product family and is designed for low active and standby power consumption.

***TEXAS: The device is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses, two 16-bit data write buses, and additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16 independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

***XS: The C55x CPU provides two multiply-accumulate (MAC) units, each capable of 17-bit x 17-bit multiplication and a 32-bit add in a single cycle. A central 40-bit arithmetic and logic unit (ALU) is supported by an additional 16-bit ALU. Use of the ALUs is under instruction set control, providing the ability to optimize parallel activity and power consumption. These resources are managed in the Address Unit (AU) and Data Unit (DU) of the C55x CPU.

***AS INSTR: The C55x CPU supports a variable byte width instruction set for improved code density. The Instruction Unit (IU) performs 32-bit program fetches from internal or external memory and queues instructions for the Program Unit (PU). The PU decodes the instructions, directs tasks to the AU and DU resources, and manages the fully protected pipeline. Predictive branching capability avoids pipeline flushes on execution of conditional instructions.

***: The GPIO functions along with the 10-bit SAR ADC to provide sufficient pins for status, interrupts, and bit I/O for keyboards, and media interfaces.

***AS INSTR: Serial media is supported through two multimedia card and secure digital (MMC and SD) peripherals, three Inter-IC Sound (I2S Bus) modules, one serial port interface (SPI) with up to four chip selects, one master and slave multichannel serial port interface (McSPI) with up to three chip selects, one multichannel serial port (McBSP), one I2C multimaster and slave interface, and a universal asynchronous receiver/transmitter (UART) interface

***AS INSTR: The device peripheral set includes an external memory interface (EMIF) that provides glueless access to asynchronous memories, such as EPROM, NOR, NAND, and SRAM, as well as to high-speed, high-density memories such as synchronous DRAM (SDRAM) and mobile SDRAM (mSDRAM).

***NS: Additional peripherals include a configurable 16-bit universal host-port interface (UHPI), a high-speed universal serial bus (USB2.0) device mode only, a real-time clock (RTC), three general-purpose timers with one configurable as a watchdog timer, and an analog phase-locked loop (APLL) clock generator.

***AS INSTRU: The device also includes a tightly coupled FFT hardware accelerate that supports 8- to 1024-point (by power of 2) real- and complex-valued FFTs and three integrated LDOs to power different sections of the device, except CVDDRTC which requires an external power source: ANA_LDO to provide 1.3 V to the SAR and power-management circuits (VDDA_ANA), DSP_LDO to provide 1.3 or 1.05 V to the DSP core (CVDD), selectable on-the-fly by software as long as operating frequency ranges are observed, and USB_LDO to provide 1.3 V to the USB core digital (USB_VDD1P3) and PHY circuits (USB_VDDA1P3).

***NS: The device is supported by the industry’s award-winning eXpressDSP, Code Composer Studio Integrated Development Environment (IDE), DSP/BIOS, Texas Instruments’ algorithm standard, and a large third-party network. Code Composer Studio IDE features code generation tools including a C Compiler and Linker, RTDX, XDS100, XDS510, XDS560 emulation device drivers, and evaluation modules. The device is also supported by the C55x DSP library which features more than 50 foundational software kernels (FIR filters, IIR filters, FFTs, and various math functions) as well as chip support libraries.

TMS32C5517AZCHA20R More Information

TMS320C5517 Fixed-Point Digital Signal Processor: OMO Electronic TMS320C5517 Fixed-Point Digital Signal Processor (DSP) is based on the TMS320C55x DSP generation CPU processor core. The C55x DSP architecture achieves high performance and low power through increased parallelism and total focus on power savings. The CPU supports an internal bus structure that is composed of one program bus, one 32-bit data read bus and two 16-bit data read buses and two 16-bit data write buses. The device also has additional buses dedicated to peripheral and DMA activity. These buses provide the ability to perform up to four 16-bit data reads and two 16-bit data writes in a single cycle. The device also includes four DMA controllers, each with 4 channels, providing data movement for 16 independent channel contexts without CPU intervention. Each DMA controller can perform one 32-bit data transfer per cycle, in parallel and independent of the CPU activity.

Processors: OMO Electronic Processors provide a comprehensive portfolio, proven software, and worldwide support enabling industry-leading automotive and industrial solutions. TI is dedicated to advancing and optimizing today’s processors to meet tomorrow’s intelligence, performance and cost requirements in automotive and industrial applications. Scalable hardware and software platforms with common code allow designers to seamlessly reuse and migrate across devices to protect future investment.

TMS32C5517AZCHA20R

Step1:Vacuum Packaging with PL

Step2:Anti-Static Bag

Step3:Packaging Boxes

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes