SN74V3680-15PEU

Mfr. #:: SN74V3680-15PEU
Description:: FIFO 16384 x 36 Synch FIFO Memory
Lifecycle:: New from this manufacturer.
Datasheet:: SN74V3680-15PEU Datasheet
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More Information:: SN74V3680-15PEU more Information SN74V3680-15PEU Product Details

Product Attribute
Attribute Value

Manufacturer:: Texas Instruments

Product Category:: FIFO

RoHS:: N

Data Bus Width:: 36 bit

Bus Direction:: Unidirectional

Memory Size:: 576 kbit

Timing Type:: Synchronous

Organization:: 16 k x 36

Number of Circuits:: 2

Maximum Clock Frequency:: 66.7 MHz

Access Time:: 10 ns

Supply Voltage - Max:: 3.45 V

Supply Voltage - Min:: 3.15 V

Supply Current - Max:: 40 mA

Minimum Operating Temperature:: 0 C

Maximum Operating Temperature:: + 70 C

Package / Case:: LQFP-128

Packaging:: Tray

Height:: 1.4 mm

Series:: SN74V3680

Width:: 14 mm

Brand:: Texas Instruments

Mounting Style:: SMD/SMT

Moisture Sensitive:: Yes

Operating Supply Voltage:: 3.3 V

Product Type:: FIFO

Factory Pack Quantity:: 72

Subcategory:: Memory & Data Storage

Unit Weight:: 0.021693 oz

Tags: SN74V368, SN74V3, SN74V, SN74, SN7

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Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes

SN74V3680-15PEU Ratings and Reviews

M***h

It came quickly. In appearance, everything is fine. I did not check in the work, but i think there will be no problems.

2019-03-11

M***a

2019-05-06

S***v

Great. Thank you.

2019-02-20

SN74V3680-15PEU Description

***as Instruments: 16384 x 36 Synchronous FIFO Memory 128-LQFP 0 to 70

***p One Stop Global: FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 36 128-Pin LQFP Tray

***i-Key: IC 16384X36 FIFO MEMORY 128LQFP

***ark: FIFO Logic IC; Frequency Max:166MHz; Supply Voltage Min:3.15V; Supply Voltage Max:3.45V; Package/Case:128-LQFP; No. of Pins:128; Operating Temperature Range:0°C to +70°C; Leaded Process Compatible:No ;RoHS Compliant: No

***AS INS: The SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 are exceptionally deep, high-speed CMOS, first-in first-out (FIFO) memories, with clocked read and write controls and a flexible bus-matching ×36/×18/×9 data flow. These FIFOs offer several key user benefits:

***AS: Bus-matching synchronous FIFOs are particularly appropriate for network, video, signal processing, telecommunications, data communications, and other applications that need to buffer large amounts of data and match buses of unequal sizes.

***AS INS: Each FIFO has a data input port (Dn) and a data output port (Qn), both of which can assume 36-bit, 18-bit, or 9-bit width, as determined by the state of external control pins input width (IW), output width (OW), and bus matching (BM) during the master-reset cycle.

***TEXAS: The input port is controlled by write-clock (WCLK) and write-enable (WEN\) inputs. Data is written into the FIFO on every rising edge of WCLK when WEN\ is asserted. The output port is controlled by read-clock (RCLK) and read-enable (REN\) inputs. Data is read from the FIFO on every rising edge of RCLK when REN\ is asserted. An output-enable (OE\) input is provided for 3-state control of the outputs.

***AS INTRUMENTS: The frequencies of the RCLK and WCLK signals can vary from 0 to fMAX, with complete independence. There are no restrictions on the frequency of one clock input with respect to the other.

***as Instruments (TI): There are two possible timing modes of operation with these devices: first-word fall-through (FWFT) mode and standard mode.

***AS INSTRUMENT: In FWFT mode, the first word written to an empty FIFO is clocked directly to the data output lines after three transitions of the RCLK signal. REN\ need not be asserted for accessing the first word. However, subsequent words written to the FIFO do require a low on REN\ for access. The state of the FWFT/SI input during master reset determines the timing mode.

***ASI: For applications requiring more data-storage capacity than a single FIFO can provide, the FWFT timing mode permits depth expansion by chaining FIFOs in series (i.e., the data outputs of one FIFO are connected to the corresponding data inputs of the next). No external logic is required.

***INS: In standard mode, the first word written to an empty FIFO does not appear on the data output lines unless a specific read operation is performed. A read operation, which consists of activating REN\ and enabling a rising RCLK edge, shifts the word from internal memory to the data output lines.

***NS: These FIFOs have five flag pins: empty flag or output ready (EF\/OR\), full flag or input ready (FF\/IR\), half-full flag (HF), programmable almost-empty flag (PAE\), and programmable almost-full flag (PAF\). The EF\ and FF\ functions are selected in standard mode. The IR\ and OR\ functions are selected in FWFT mode. HF\, PAE\, and PAF\ are always available for use, regardless of timing mode.

***AS: PAE\ and PAF\ can be programmed independently to switch at any point in memory. Programmable offsets determine the flag-switching threshold and can be loaded by parallel or serial methods. Eight default offset settings are also provided, so that PAE\ can be set to switch at a predefined number of locations from the empty boundary. The PAF\ threshold also can be set at similar predefined values from the full boundary. The default offset values are set during master reset by the state of the FSEL0, FSEL1, and LD\.

***as Instruments (TI): For serial programming, SEN\, together with LD\, loads the offset registers via the serial input (SI) on each rising edge of WCLK. For parallel programming, WEN\, together with LD\, loads the offset registers via Dn on each rising edge of WCLK. REN\, together with LD\, can read the offsets in parallel from Qn on each rising edge of RCLK, regardless of whether serial parallel offset loading has been selected.

***AS INSRUMENT: During master reset (MRS\), the read and write pointers are set to the first location of the FIFO. The FWFT pin selects standard mode or FWFT mode.

***TEXAS: Partial reset (PRS\) also sets the read and write pointers to the first location of the memory. However, the timing mode, programmable-flag programming method, and default or programmed offset settings existing before partial reset remain unchanged. The flags are updated according to the timing mode and offsets in effect. PRS\ is useful for resetting a device in mid-operation, when reprogramming programmable flags would be undesirable.

***AS INS: Also, the timing modes of PAE\ and PAF\ outputs can be selected. Timing modes can be set to be either asynchronous or synchronous for PAE\ and PAF\.

***XS: If the asynchronous PAE\/PAF\ configuration is selected, PAE\ is asserted low on the low-to-high transition of RCLK. PAE\ is reset to high on the low-to-high transition of WCLK. Similarly, PAF\ is asserted low on the low-to-high transition of WCLK, and PAF\ is reset to high on the low-to-high transition of RCLK.

***AS: If the synchronous PAE\/PAF\ configuration is selected , the PAE\ is asserted and updated on the rising edge of RCLK only, and not WCLK. Similarly, PAF\ is asserted and updated on the rising edge of WCLK only, and not RCLK. The mode desired is configured during master reset by the state of the programmable flag mode (PFM).

***: The retransmit function allows data to be reread from the FIFO more than once. A low on the retransmit (RT\) input during a rising RCLK edge initiates a retransmit operation by setting the read pointer to the first location of the memory array. Zero-latency retransmit timing mode can be selected using the retransmit timing mode (RM). During master reset, a low on RM selects zero-latency retransmit. A high on RM during master reset selects normal latency.

***ASI: If zero-latency retransmit operation is selected, the first data word to be retransmitted is placed on the output register, with respect to the same RCLK edge that initiated the retransmit, if RT\ is low.

***ASI: See Figures 11 and 12 for normal latency retransmit timing. See Figures 13 and 14 for zero-latency retransmit timing.

***ASI: The devices can be configured with different input and output bus widths (see Table 1).

***AS INSTRUMENTS INC: A big-endian/little-endian data word format is provided. This function is useful when data is written into the FIFO in long-word (×36/×18) format and read out of the FIFO in small-word (×18/×9) format. If big-endian mode is selected, the most significant byte (MSB) (word) of the long word written into the FIFO is read out of the FIFO first, followed by the least-significant byte (LSB). If little-endian format is selected, the LSB of the long word written into the FIFO is read out first, followed by the MSB. The mode desired is configured during master reset by the state of the big-endian/little-endian (BE\) pin (see Figure 4 for the bus-matching byte arrangement).

***AS INSTRUMENTS INCORPORATED: The interspersed/noninterspersed parity (IP) bit function allows the user to select the parity bit in the word loaded into the parallel port (D0-Dn) when programming the flag offsets. If interspersed-parity mode is selected, the FIFO assumes that the parity bit is located in bit positions D8, D17, D26, and D35 during the parallel programming of the flag offsets. If noninterspersed-parity mode is selected, D8, D17, and D26 are assumed to be valid bits and D32, D33, D34, and D35 are ignored. Interspersed parity mode is selected during master reset by the state of the IP input. Interspersed parity control has an effect only during parallel programming of the offset registers. It does not affect data written to and read from the FIFO.

***ASI: The SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, and SN74V3690 are fabricated using high-speed submicron CMOS technology, and are characterized for operation from 0°C to 70°C.

Market price

Part #	Description	Stock	Price
SN74V3680-15PEU DISTI # 29459549	FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 36 128-Pin LQFP Tray RoHS: Compliant	432	288:$22.6680 144:$23.9274 72:$25.3349
SN74V3680-15PEU DISTI # SN74V3680-15PEU-ND	IC 16384X36 FIFO MEMORY 128LQFP RoHS: Compliant Min Qty: 72 Container: Tray	Temporarily Out of Stock	72:$30.3629
SN74V3680-15PEU DISTI # SN74V3680-15PEU	FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 36 128-Pin LQFP Tray (Alt: SN74V3680-15PEU) RoHS: Compliant Min Qty: 1 Container: Tray	Europe - 48	1:€26.7900 10:€25.4900 25:€24.1900 50:€23.0900 100:€22.0900 500:€21.0900 1000:€20.2900
SN74V3680-15PEU DISTI # SN74V3680-15PEU	FIFO Mem Sync Dual Depth/Width Uni-Dir 16K x 36 128-Pin LQFP Tray - Trays (Alt: SN74V3680-15PEU) RoHS: Not Compliant Min Qty: 72 Container: Tray	Americas - 0	72:$28.2900 144:$27.6900 288:$26.5900 432:$25.8900 720:$25.4900
SN74V3680-15PEU DISTI # 595-SN74V3680-15PEU	FIFO 16384 x 36 Synch FIFO Memory RoHS: Not compliant	0	1:$32.8300 5:$31.4700 10:$30.2800 25:$28.9200 100:$25.8600 250:$24.6700

Image	Part #	Description
	Mfr.#: SN74V3680-15PEU OMO.#: OMO-SN74V3680-15PEU	FIFO 16384 x 36 Synch FIFO Memory
	Mfr.#: SN74V3690-7PEU OMO.#: OMO-SN74V3690-7PEU	FIFO 32768 x 36 Synch FIFO Memory
	Mfr.#: SN74V3660-15PEU OMO.#: OMO-SN74V3660-15PEU	FIFO 4096 x 36 Synch FIFO Memory
	Mfr.#: SN74V3680-10PEU OMO.#: OMO-SN74V3680-10PEU	FIFO 16384 x 36 Synch FIFO Memory
	Mfr.#: SN74V3680-15PEU OMO.#: OMO-SN74V3680-15PEU-TEXAS-INSTRUMENTS	FIFO 16384 x 36 Synch FIFO Memory
	Mfr.#: SN74V3650-10PEU OMO.#: OMO-SN74V3650-10PEU-TEXAS-INSTRUMENTS	IC 2048X36 FIFO MEMORY 128LQFP
	Mfr.#: SN74V3650-15PEU OMO.#: OMO-SN74V3650-15PEU-TEXAS-INSTRUMENTS	IC 2048X36 FIFO MEMORY 128LQFP
	Mfr.#: SN74V3650-6PEU OMO.#: OMO-SN74V3650-6PEU-TEXAS-INSTRUMENTS	IC 2048X36 FIFO MEMORY 128LQFP
	Mfr.#: SN74V3670-15PEU OMO.#: OMO-SN74V3670-15PEU-TEXAS-INSTRUMENTS	IC 8192X36 FIFO MEMORY 128LQFP
	Mfr.#: SN74V3680-10PEU OMO.#: OMO-SN74V3680-10PEU-TEXAS-INSTRUMENTS	IC 16384X36 FIFO MEMORY 128LQFP