CD74HC175E

Mfr. #:: CD74HC175E
Description:: Flip Flops Quad HS CMOS
Lifecycle:: New from this manufacturer.
Datasheet:: CD74HC175E Datasheet
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More Information:: CD74HC175E more Information CD74HC175E Product Details

Product Attribute
Attribute Value

Manufacturer:: Texas Instruments

Product Category:: Flip Flops

RoHS:: Y

Number of Circuits:: 4

Logic Family:: HC

Logic Type:: D-Type Flip-Flop

Polarity:: Inverting/Non-Inverting

Input Type:: CMOS

Output Type:: CMOS

Propagation Delay Time:: 175 ns

High Level Output Current:: - 5.2 mA

Low Level Output Current:: 5.2 mA

Supply Voltage - Min:: 2 V

Supply Voltage - Max:: 6 V

Minimum Operating Temperature:: - 55 C

Maximum Operating Temperature:: + 125 C

Mounting Style:: Through Hole

Package / Case:: PDIP-16

Packaging:: Tube

Function:: Quad High Speed CMOS

Height:: 4.57 mm

Length:: 19.3 mm

Operating Temperature Range:: - 55 C to + 125 C

Quiescent Current:: 8 uA

Series:: CD74HC175

Width:: 6.35 mm

Brand:: Texas Instruments

Number of Channels:: 4

Number of Input Lines:: 4

Number of Output Lines:: 4

Operating Supply Voltage:: 6 V

Product Type:: Flip Flops

Reset Type:: Master Reset

Factory Pack Quantity:: 25

Subcategory:: Logic ICs

Unit Weight:: 0.033570 oz

Tags: CD74HC175E, CD74HC175, CD74HC17, CD74HC1, CD74HC, CD74H, CD74, CD7

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CD74HC175E Description

***inecomponents.com: Flip Flop D-Type Bus Interface Pos-Edge 1-Element 16-Pin PDIP Tube

***i-Key Marketplace: IC FF D-TYPE SNGL 4BIT 16DIP

***fin: Integrated Circuit Mos 74HC175/CD74HC175E HARRIS HC

***as Instruments Inc.: The HC175 and HCT175 are high speed Quad D-type Flip-Flops with individual D-inputs and Q, Q\ complementary outputs. The devices are fabricated using silicon gate CMOS technology. They have the low power consumption advantage of standard CMOS ICs and the ability to drive 10 LSTTL devices.

***AS INSTRU: Information at the D input is transferred to the Q, Q\ outputs on the positive going edge of the clock pulse. All four Flip-Flops are controlled by a common clock (CP) and a common reset (MR\). Resetting is accomplished by a low voltage level independent of the clock. All four Q outputs are reset to a logic 0 and all four Q\ outputs to a logic 1.

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On Order:: 1984
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CD74HC175E

Step1:Vacuum Packaging with PL

Step2:Anti-Static Bag

Step3:Packaging Boxes

Step1:
Vacuum Packaging with PL

Step2:
Anti-Static Bag

Step3:
Packaging Boxes