SN74SSTUB32866ZWLR

Mfr. #:: SN74SSTUB32866ZWLR
Description:: Registers 25B Configurable Registered Buffer
Lifecycle:: New from this manufacturer.
Datasheet:: SN74SSTUB32866ZWLR Datasheet
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More Information:: SN74SSTUB32866ZWLR more Information SN74SSTUB32866ZWLR Product Details

Product Attribute
Attribute Value

Manufacturer:: Texas Instruments

Product Category:: Registers

RoHS:: Y

Logic Type:: CMOS

Logic Family:: SSTU

Number of Circuits:: 1

Maximum Clock Frequency:: 410 MHz

Propagation Delay Time:: 0.8 ns

High Level Output Current:: - 8 mA

Low Level Output Current:: 8 mA

Supply Voltage - Max:: 1.9 V

Supply Voltage - Min:: 1.7 V

Minimum Operating Temperature:: - 40 C

Maximum Operating Temperature:: + 85 C

Package / Case:: BGA-96

Packaging:: Reel

Height:: 0.89 mm

Input Type:: Single-Ended

Length:: 13.5 mm

Series:: SN74SSTUB32866

Width:: 5.5 mm

Brand:: Texas Instruments

Mounting Style:: SMD/SMT

Number of Channels:: 25

Number of Input Lines:: 25

Number of Output Lines:: 25

Moisture Sensitive:: Yes

Operating Supply Voltage:: 1.8 V

Polarity:: Non-Inverting

Product Type:: Registers

Reset Type:: Asynchronous

Factory Pack Quantity:: 1000

Subcategory:: Logic ICs

Triggering Type:: Positive-Edge/Negative-Edge

Part # Aliases:: HPA00322ZWLR

Unit Weight:: 0.006349 oz

Tags: SN74SSTUB, SN74SSTU, SN74SST, SN74SS, SN74S, SN74, SN7

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SN74SSTUB32866ZWLR Description

***as Instruments: 25-bit configurable registered buffer with address-parity test 96-BGA -40 to 85

*** Stop Electro: D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, TTL, PBGA96

***ical: Registered Buffer Single-Element 25-CH CMOS 96-Pin BGA T/R

***AS INS: This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads.

***ASIN: All inputs are SSTL_18, except the reset (RESET) and control (Cn) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications, except the open-drain error (QERR) output.

***AS: The SN74SSTUB32866 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low.

***AS: The SN74SSTUB32866 accepts a parity bit from the memory controller on the parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs (D2-D3, D5-D6, D8-D25 when C0 = 0 and C1 = 0; D2-D3, D5-D6, D8-D14 when C0 = 0 and C1 = 1; or D1-D6, D8-D13 when C0 = 1 and C1 = 1) and indicates whether a parity error has occurred on the open-drain QERR pin (active low). The convention is even parity; i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs, combined with the parity input bit. To calculate parity, all DIMM-independent data inputs must be tied to a known logic state.

***: When used as a single device, the C0 and C1 inputs are tied low. In this configuration, parity is checked on the PAR_IN input signal, which arrives one cycle after the input data to which it applies. Two clock cycles after the data are registered, the corresponding partial-parity-out (PPO) and QERR signals are generated.

***AS INSTRUMENT: When used in pairs, the C0 input of the first register is tied low, and the C0 input of the second register is tied high. The C1 input of both registers are tied high. Parity, which arrives one cycle after the data input to which it applies, is checked on the PAR_IN input signal of the first device. Two clock cycles after the data are registered, the corresponding PPO and QERR signals are generated on the second device. The PPO output of the first register is cascaded to the PAR_IN of the second SN74SSTUB32866. The QERR output of the first SN74SSTUB32866 is left floating, and the valid error information is latched on the QERR output of the second SN74SSTUB32866.

***: If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or until RESET is driven low. If two or more consecutive parity errors occur, the QERR output is driven low and latched low for a clock duration equal to the parity-error duration or until RESET is driven low. The DIMM-dependent signals (DCKE, DCS, DODT, and CSR) are not included in the parity-check computation.

***OMO Electronic: The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the A6, D6, and H6 terminals are driven low and are do-not-use (DNU) pins.

***AS INSRUMENT: In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is cleared, and the data outputs are driven low quickly, relative to the time required to disable the differential input receivers. However, when coming out of reset, the register becomes active quickly, relative to the time required to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the SN74SSTUB32866 ensures that the outputs remain low, thus ensuring there will be no glitches on the output.

***as Instr.: To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up.

***: The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low, except QERR. The LVCMOS RESET and Cn inputs always must be held at a valid logic high or low level.

***AS INSTR: The device also supports low-power active operation by monitoring both system chip select (DCS and CSR) inputs and gates the Qn and PPO outputs from changing states when both DCS and CSR inputs are high. If either DCS or CSR input is low, the Qn and PPO outputs function normally. Also, if the internal low-power signal (LPS1) is high (one cycle after DCS and CSR go high), the device gates the QERR output from changing states. If LPS1 is low, the QERR output functions normally. The RESET input has priority over the DCS and CSR control and, when driven low, forces the Qn and PPO outputs low and forces the QERR output high. If the DCS control functionality is not desired, the CSR input can be hard-wired to ground, in which case the setup-time requirement for DCS is the same as for the other D data inputs. To control the low-power mode with DCS only, the CSR input should be pulled up to VCC through a pullup resistor.

***ASIN: The two VREF pins (A3 and T3) are connected together internally by approximately 150. However, it is necessary to connect only one of the two VREF pins to the external VREF power supply. An unused VREF pin should be terminated with a VREF coupling capacitor.

SN74SSTUB32866ZWLR More Information

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Market price

Part #	Description	Stock	Price
SN74SSTUB32866ZWLR DISTI # V98:2334_07360501	Registered Buffer Single 25-CH CMOS 96-Pin BGA T/R RoHS: Compliant	1000	1000:$6.9590 500:$7.0320 250:$8.0960 100:$8.1800 25:$9.8630 10:$9.9670 1:$11.0680
SN74SSTUB32866ZWLR DISTI # 296-22579-1-ND	IC CONFIG REG BUFFER 25BIT 96BGA RoHS: Compliant Min Qty: 1 Container: Cut Tape (CT)	1092In Stock	500:$7.5419 100:$8.6610 10:$10.4610 1:$11.5800
SN74SSTUB32866ZWLR DISTI # 296-22579-6-ND	IC CONFIG REG BUFFER 25BIT 96BGA RoHS: Compliant Min Qty: 1 Container: Digi-Reel®	1092In Stock	500:$7.5419 100:$8.6610 10:$10.4610 1:$11.5800
SN74SSTUB32866ZWLR DISTI # 296-22579-2-ND	IC CONFIG REG BUFFER 25BIT 96BGA RoHS: Compliant Min Qty: 1000 Container: Tape & Reel (TR)	Temporarily Out of Stock	1000:$6.3774
SN74SSTUB32866ZWLR DISTI # 25830433	Registered Buffer Single 25-CH CMOS 96-Pin BGA T/R RoHS: Compliant	1000	1000:$6.9590 500:$7.0320 250:$8.0960 100:$8.1800 25:$9.8630 10:$9.9670 2:$11.0680
SN74SSTUB32866ZWLR DISTI # SN74SSTUB32866ZWLR	Registered Buffer Single 25-CH CMOS 96-Pin BGA T/R (Alt: SN74SSTUB32866ZWLR) RoHS: Compliant Min Qty: 1000 Container: Tape and Reel	Asia - 0
SN74SSTUB32866ZWLR DISTI # SN74SSTUB32866ZWLR	Registered Buffer Single 25-CH CMOS 96-Pin BGA T/R - Tape and Reel (Alt: SN74SSTUB32866ZWLR) RoHS: Compliant Min Qty: 1000 Container: Reel	Americas - 0	1000:$6.7900 2000:$6.4900 4000:$6.2900 6000:$5.9900 10000:$5.8900
SN74SSTUB32866ZWLR DISTI # SN74SSTUB32866ZWLR	Registered Buffer Single 25-CH CMOS 96-Pin BGA T/R (Alt: SN74SSTUB32866ZWLR) RoHS: Compliant Min Qty: 1000 Container: Tape and Reel	Europe - 0	1000:€7.8900 2000:€6.9900 4000:€6.1900 6000:€5.8900 10000:€5.5900
SN74SSTUB32866ZWLR	25-Bit Configurable Registered Buffer With Address-Parity Test	4000	1000:$5.3700 750:$5.4800 500:$6.3300 250:$7.2800 100:$7.8000 25:$8.6900 10:$9.3100 1:$10.3500
SN74SSTUB32866ZWLR DISTI # 595-74SSTUB32866ZWLR	Registers 25B Configurable Registered Buffer RoHS: Compliant	0	1000:$6.3800
HPA00322ZWLR DISTI # 595-HPA00322ZWLR	Registers 25-Bit Configurable Registered Buffer With Address-Parity Test 96-BGA -40 to 85 RoHS: Compliant	0
SN74SSTUB32866ZWLR	D Flip-Flop, SSTU Series, 1-Func, Positive Edge Triggered, 25-Bit, True Output, TTL, PBGA96 RoHS: Compliant	37976	1000:$6.2100 500:$6.5400 100:$6.8100 25:$7.1000 1:$7.6400
SN74SSTUB32866ZWLR	RoHS: Not Compliant	1000	1000:$6.2100 500:$6.5400 100:$6.8100 25:$7.1000 1:$7.6400
SN74SSTUB32866ZWLR DISTI # C1S746201930503	Registered Buffer Single 25-CH CMOS 96-Pin BGA T/R RoHS: Compliant	1000	250:$8.0960 100:$8.1800 25:$9.8630 10:$9.9670 1:$11.0680

Image	Part #	Description
	Mfr.#: SN74SSTUB32866ZWLR OMO.#: OMO-SN74SSTUB32866ZWLR	Registers 25B Configurable Registered Buffer
	Mfr.#: SN74SSTUB32866ZKER OMO.#: OMO-SN74SSTUB32866ZKER	Registers 25-B Con Reg Buffer
	Mfr.#: SN74SSTUB32864ZKER OMO.#: OMO-SN74SSTUB32864ZKER	Registers 25-Bit Configurable Registered Buffer
	Mfr.#: SN74SSTUB32866ZKER OMO.#: OMO-SN74SSTUB32866ZKER-TEXAS-INSTRUMENTS	Registers 25-B Con Reg Buffe
	Mfr.#: SN74SSTUB32864ZKER OMO.#: OMO-SN74SSTUB32864ZKER-TEXAS-INSTRUMENTS	Registers 25-Bit Configurable Registered Buffe
	Mfr.#: SN74SSTUB32866ZWLR OMO.#: OMO-SN74SSTUB32866ZWLR-TEXAS-INSTRUMENTS	Registers 25B Configurable Registered Buffe

SN74SSTUB32866ZWLR

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