LT2940
8
2940f
PIN FUNCTIONS
CMPOUT (Pin 1): Inverting Open-Collector Comparator
Output. When the LATCH pin’s state does not override the
comparator, CMPOUT pulls low when CMP
+
> 1.24V. The
pull-down shuts off when CMP
+
< 1.21V, or V
CC
< 2.5V or
when the LATCH pin is low. CMPOUT may be pulled up to
36V maximum. Do not sink more than 22mA DC.
CMPOUT (Pin 2): Noninverting Open-Collector Comparator
Output. When the LATCH pin’s state does not override the
comparator, CMPOUT pulls low when CMP
+
< 1.21V, or
V
CC
< 2.5V, or when the LATCH pin is low. The pull-down
shuts off when CMP
+
> 1.24V. CMPOUT may be pulled up
to 36V maximum. Do not sink more than 22mA DC.
CMP
+
(Pin 3): Positive Comparator Input. The integrated
comparator resolves to high when the pin voltage exceeds
the 1.24V internal reference. The comparator input has
35mV of negative hysteresis, which makes its falling trip
point approximately 1.21V. Do not exceed 36V. Tie CMP
+
to GND if unused.
PMON (Pin 4): Proportional-to-Power Monitor Output. This
push-pull output sources or sinks a current proportional
to the product of the voltage sense and current sense
inputs. A resistor from PMON to GND creates a positive
voltage when the power product is positive. The full-scale
output of ±200µA is generated for a sense input product
of ±0.4V
2
. Do not exceed V
CC
+ 1V, up to 16V maximum.
Tie PMON to GND if unused.
IMON (Pin 5): Proportional-to-Current Monitor Output.
This push-pull output sources or sinks a current propor-
tional to the voltage at the current sense input, which is
typically generated by a sense resistor that measures a
current. A resistor from IMON to GND creates a positive
voltage when the sensed current is positive. The full-scale
output of ±200µA is generated by a current sense input
of ±200mV. Do not exceed V
CC
+ 1V, up to 16V maximum.
Tie IMON to GND if unused.
GND (Pin 6): Device Ground.
V
+
, V
–
(Pins 8, 7): Voltage Sense Inputs. The voltage
difference between these pins is the voltage input factor
to the power calculation multiplier. The difference may be
positive or negative, but both pin voltages must be at or
above GND – 100mV. The input differential voltage range
is ±8V. Do not exceed 36V on either pin.
LATCH (Pin 9): Comparator Mode Input. Conditions at this
three-state input pin control the comparator’s behavior.
When LATCH is open, the comparator’s outputs track its
input conditions (with hysteresis). When LATCH is held
above 2.5V, the comparator’s outputs latch when CMP
+
exceeds 1.24V (CMPOUT open, CMPOUT pull-down). While
LATCH ≤ 0.5V or V
CC
< 2.5V, the comparator’s outputs clear
(CMPOUT pull-down, CMPOUT open) regardless of the
CMP
+
pin voltage. The LATCH pin high impedance input
state tolerates ±10µA of leakage current. Bypass this pin
to GND to compensate for high dV/dt on adjacent pins.
Do not exceed 100V on this pin.
I
+
, I
–
(Pins 11, 10): Current Sense Inputs. The voltage differ-
ence at these pins represents the current input factor to the
power calculation multiplier and to the current scaler. The
difference may be positive or negative, but both pin voltages
must be at least 4V and no more than 80V above GND,
completely independent of the V
CC
voltage. Both pins sink
approximately 100µA of bias current in addition to having
an effective 5k shunt between them. The input differential
voltage range is ±200mV. Do not exceed ±36V differ-
entially or 100V on either pin.
V
CC
(Pin 12): Voltage Supply. The voltage supply operat-
ing range is 6V to 80V. When operating with V
CC
> 15V,
package heating can be reduced by adding an external
series dropping resistor. Bypass this pin to GND to improve
supply rejection at frequencies above 10kHz as needed.
Do not exceed 100V on this pin.
Exposed Pad (Pin 13 in DFN Package): The exposed pad
may be left open or connected to device ground. For best
thermal performance, the exposed pad must be soldered
to the PCB.
