ICS1894-43
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 4
ICS1894-43 REV A 030112
Notes:
1. AIO: Analog input/output PAD.
IO: Digital input/output.
IN/Ipu: Digital input with internal 20k pull-up.
IN/Ipd: Digital input with internal 20k pull-down.
IO/Ipu: Digital input/output with internal 20k pull-up.
IO/Ipd: Digital input/output with internal 20k pull-down.
2. RMII Rx Mode: The RXD[1:0] bits are synchronous with REFIN. For each clock period in which CRS_DV is
asserted, two bits of recovered data are sent from the PHY to the MAC.
3. RMII Tx Mode: The TXD[1:0] bits are synchronous with REFIN. For each clock period in which TX_EN is
asserted, two bits of data are received by the PHY from the MAC.
33 TXD1 Input Transmit data Bit 1 in RMII mode.
34 VSS Ground Connect to ground.
35 VSS Ground Connect to ground.
36 NC No connect.
37 REF_IN Input 50MHz clock input for RMII mode.
38 P4/LED2 IO/Ipu PHY address Bit 4 as input (always latched high during power on reset and
hardware reset) and LED # 2 as output
39 P0/LED0 IO PHY address Bit 0 as input (during power on reset and hardware reset) and LED #
0(function configurable, default is "activity/no activity") as output
40 P1/ISO/LED1 IO PHY address Bit 1 as input (during power on reset and hardware reset) and LED #
1 (function configurable, default is "10/100 mode") as output
Pin
Number
Pin
Name
Pin
Type
Pin Description
ICS1894-43
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 5
ICS1894-43 REV A 030112
Strapping Options
1. IO/Ipu = Digital Input with internal 20k pull-up during power on reset/hardware reset; output pin otherwise.
2. If RXTRI/RXD1 pin is latched high during power on reset/hardware reset, P1/ISO/LED1 functions as RX real time
isolation control input after latch and LED1 function will be disabled.
3. When Autonegotiation is enabled, the speed will be determined by the result of Autonegotiation between the link
partners. When Autonegotiation is not enabled, the speed will be determined by the state of either a real-time
pin (pin 24) or a register bit (00.13); whether pin 24 or Register00.13 is in control in this case is determined by
register bit 19.14, which in turn has a latched-in default value from pin 16.
Pin
Number
Pin
Name
Pin
Type
1
Pin Function
16 HWSW IO/Ipd
Hardware pin select enable. Active during power-on and hardware reset.
17 REGPIN IO/Ipd
Full register access enable. Active during power-on and hardware reset.
18 AMDIX IO/Ipu
1 = AMDIX enable
0 = AMDIX disable
38 P4/LED2 IO/Ipu The PHY address is set by P[4:0] at power-on reset. P0 and P1 must have external
pull-up or pull-down to set address at start up.
19 P3 IO/Ipd
12 P2/INT IO/Ipd
40 P1/ISO/LED1 IO
39 P0/LED0 IO
21 LED4 IO/Ipd LED4 output
.
20 RXTRI/RXD1 IO/Ipd
1=Realtime receiver isolation enable
2
;
0=RX output enable
22 FDPX/RXD0 IO/Ipu
1=Full duplex
0=Half duplex
Ignored if Auto negotiation is enabled
23 RMII/RXDV IO/Ipd
1=RMII mode
0=mode not supported
24 RTSPEED
3
IO/Ipu
1=100M mode
0=10M mode
26 ANSEL IO/Ipu
1=Enable auto negotiation
0=Disable auto negotiation
27 NOD/RXER IO/Ipd
0=Node mode
1=repeater mode
28 SPEED
3
IO/Ipu
1=100M mode
0=10M mode
Ignored if Auto negotiation is enabled
32 LED3 IO/Ipu LED3 output
ICS1894-43
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE PHYCEIVER
IDT®
10BASE-T/100BASE-TX INTEGRATED PHYCEIVER WITH RMII INTERFACE 6
ICS1894-43 REV A 030112
Application Schematic

1894K-43LF

Mfr. #:
Manufacturer:
Description:
IC CONTROLLER ETHERNET 40VFQFPN
Lifecycle:
New from this manufacturer.
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