7
CLOCK
8 DATA BITS
+5V
15
16
14
8
1-7, 9
LE
D0 - D7
V
DD
COMP
V
SS
CA3338
V
OUT
V
REF
+
V
EE
12
13
11
10
+5V
+2.5V
-2.5V
R1
R2
PROBE TIP
REMOTE
V
OUT
R3
V
REF
-
OR BNC
CONNECTOR
DIGITAL
GROUND
ANALOG
GROUND
+
+
+
FIGURE 5. CA3338 DYNAMIC TEST CIRCUIT
FUNCTION CONNECTOR R1 R2 R3 V
OUT (P-P)
Oscilloscope Display Probe Tip 82 62 N/C 1V
Match 93 Cable BNC 75 160 93 1V
Match 75 Cable BNC 18 130 75 1V
Match 50Cable BNC Short 75 50 0 79V
NOTES:
3. V
OUT(P-P)
is approximate, and will vary as R
OUT
of D/A varies.
4. All drawn capacitors are 0.1µF multilayer ceramic/4.7µF tantalum.
5. Dashed connections are for unipolar operation. Solid connection are for bipolar operation.
NOTES:
1. Both V
REF
+
pin and 392 resistor should be
bypassed within
1
/
4
inch.
2. Keep nodal capacitance at CA3450 pin 3 as
low as possible.
3. V
OUT
Range = ±3V at CA3450.
CLOCK
8 DATA
+5V
15
16
14
8
1-7, 9
LE
D0 - D7
V
DD
COMP
V
SS
CA3338
V
OUT
V
REF
+
V
EE
12
13
11
10
R
V
REF
-
R
11
UP TO 5 OUTPUT LINES
FOR R = 75, 3 LINES
FOR R = 50
V
OUT
1
V
OUT
N
+3.00V AT 25mA
4.7µF
TAN
4.7µF TAN
4.7µF TAN
4.7µF
TAN
0.1µF CER.
0.1µF
CER.
0.1µF
CER.
0.1µF CER.
14
+6V
-6V
392
392
1%
10k
1k
3
4, 5, 12, 13
R
R
+
+
+
+
V
OUT
= ±1.5V
PEAK
6
7, 8
9
+
-
CA3450
ADJUST
OFFSET
5pF
BITS
1%
FIGURE 6. CA3338 AND CA3450 FOR DRIVING MULTIPLE COAXIAL LINES
CA3338, CA3338A
8
CA3338, CA3338A
Applications
The output of the CA3338 can be resistively divided to match a
doubly terminated 50 or 75 line, although peak-to-peak
swings of less than 1V may result. The output magnitude will
also vary with the converter’s output impedance. Figure 5
shows such an application. Note that because of the HCT input
structure, the CA3338 could be operated up to +7.5V V
DD
and
V
REF
+ supplies and still accept 0V to 5V CMOS input voltages.
If larger voltage swings or better accuracy is desired, a high
speed output buffer, such as the HA-5033, HA-2542, or
CA3450, can be employed. Figure 6 shows a typical
application, with the output capable of driving ±2V into
multiple 50terminated lines.
Operating and Handling Considerations
HANDLING
All inputs and outputs of CMOS devices have a network for
electrostatic protection during handling. Recommended
handling practices for CMOS devices are described in
AN6525. “Guide to Better Handling and Operation of CMOS
Integrated Circuits.
OPERATING
OPERATING VOLTAGE
During operation near the maximum supply voltage limit,
care should be taken to avoid or suppress power supply
turn-on and turn-off transients, power supply ripple, or
ground noise; any of these conditions must not cause the
absolute maximum ratings to be exceeded.
INPUT SIGNALS
To prevent damage to the input protection circuit, input
signals should never be greater than V
DD
nor less than V
SS
.
Input currents must not exceed 20mA even when the power
supply is off.
UNUSED INPUTS
A connection must be provided at every input terminal. All
unused input terminals must be connected to either V
CC
or
GND, whichever is appropriate.
TABLE 1. OUTPUT VOLTAGE vs INPUT CODE AND V
REF
V
REF
+
V
REF
-
STEP SIZE
5.12V
0
0.0200V
5.00V
0
0.0195V
4.608V
0
0.0180V
2.56V
-2.56V
0.0200V
2.50V
-2.50V
0.0195V
Input Code
11111111
2
=FF
HEX
11111110
2
=FE
HEX
5.1000V
5.0800
4.9805V
4.9610
4.5900V
4.5720
2.5400V
2.5200
2.4805V
2.4610
10000001
2
=81
HEX
10000000
2
=80
HEX
01111111
2
=7F
HEX
2.5800
2.5600
2.5400
2.5195
2.5000
2.4805
2.3220
2.3040
2.2860
0.0200
0.0000
- 0.0200
0.0195
0.0000
-0.0195
00000001
2
=01
HEX
00000000
2
=00
HEX
0.0200
0.0000
0.0195
0.0000
0.0180
0.0000
-2.5400
-2.5600
-2.4805
-2.5000
9
CA3338, CA3338A
Dual-In-Line Plastic Packages (PDIP)
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English and
Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in JE-
DEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and are measured with the leads constrained to be perpendic-
ular to datum .
7. e
B
and e
C
are measured at the lead tips with the leads unconstrained.
e
C
must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 - 1.14mm).
e
A
-C-
C
L
E
e
A
C
e
B
e
C
-B-
E1
INDEX
12 3 N/2
N
AREA
SEATING
BASE
PLANE
PLANE
-C-
D1
B1
B
e
D
D1
A
A2
L
A1
-A-
0.010 (0.25) C AM BS
E16.3 (JEDEC MS-001-BB ISSUE D)
16 LEAD DUAL-IN-LINE PLASTIC PACKAGE
SYMBOL
INCHES MILLIMETERS
NOTESMIN MAX MIN MAX
A - 0.210 - 5.33 4
A1 0.015 - 0.39 - 4
A2 0.115 0.195 2.93 4.95 -
B 0.014 0.022 0.356 0.558 -
B1 0.045 0.070 1.15 1.77 8, 10
C 0.008 0.014 0.204 0.355 -
D 0.735 0.775 18.66 19.68 5
D1 0.005 - 0.13 - 5
E 0.300 0.325 7.62 8.25 6
E1 0.240 0.280 6.10 7.11 5
e 0.100 BSC 2.54 BSC -
e
A
0.300 BSC 7.62 BSC 6
e
B
- 0.430 - 10.92 7
L 0.115 0.150 2.93 3.81 4
N16 169
Rev. 0 12/93

CA3338AE

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
IC DAC 8BIT V-OUT 16DIP
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

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