Fail-Safe
The MAX9173 fail-safe drives the receiver output high
when the differential input is:
Open
Undriven and shorted
Undriven and terminated
Without fail-safe, differential noise at the input may
switch the receiver and appear as data to the receiving
system. An open input occurs when a cable and termi-
nation are disconnected. An undriven, terminated input
occurs when a cable is disconnected with the termina-
tion still connected across the receiver inputs or when
the driver of a receiver is in high impedance. An undriv-
en, shorted input can occur due to a shorted cable.
“In-Path” vs. “Parallel” Fail-Safe
The MAX9173 has in-path fail-safe that is compatible
with in-path fail-safe receivers, such as the
DS90LV048A. Refer to the MAX9121/MAX9122 data
sheet for pin-compatible receivers with parallel fail-safe
and lower jitter. Refer to the MAX9130 data sheet for a
single LVDS receiver with parallel fail-safe in an SC70
package.
The MAX9173 with in-path fail-safe is designed with a
+45mV input offset voltage, a 2.5µA current source
between V
CC
and the noninverting input, and a 5µA
current sink between the inverting input and ground
(Figure 1). If the differential input is open, the 2.5µA
current source pulls the input to approximately V
CC
-
0.8V and the 5µA current sink pulls the inverting input
to ground, which drives the receiver output high. If the
differential input is shorted or terminated with a typical
value termination resistor, the +45mV offset drives the
receiver output high. If the input is terminated and float-
ing, the receiver output is driven high by the +45mV off-
set, and the 2:1 current sink to current source ratio
(5µA:2.5µA) pulls the inputs to ground. This can be an
advantage when switching between drivers on a multi-
point bus because the change in common-mode volt-
age from ground to the typical driver offset voltage of
1.2V is not as much as the change from V
CC
to 1.2V
(parallel fail-safe pulls the bus to V
CC
).
ESD Protection
ESD-protection structures are incorporated on all pins
to protect against electrostatic discharges encountered
during handling and assembly. The receiver inputs of
the MAX9173 have ±7.0kV of protection against static
electricity (per Human Body Model).
Figure 6a shows the Human Body Model, and Figure
6b shows the current waveform it generates when dis-
charged into a low-impedance load. This model con-
sists of a 100pF capacitor charged to the ESD test volt-
age, which is then discharged into the test device
through a 1.5k resistor.
Applications Information
Differential Traces
Input trace characteristics affect the performance of the
MAX9173. Use controlled-impedance board traces. For
point-to-point connections, match the receiver input ter-
mination resistor to the differential characteristic imped-
ance of the board traces.
Eliminate reflections and ensure that noise couples as
common mode by running the differential traces close
together. Reduce skew by matching the electrical
length of the traces. Excessive skew can result in a
degradation of magnetic field cancellation.
Each channels differential signals should be routed
close to each other to cancel their external magnetic
field. Maintain a constant distance between the differ-
ential traces to avoid discontinuities in differential
impedance. Minimize the number of vias to further pre-
vent impedance discontinuities.
Cables and Connectors
LVDS transmission media typically have controlled dif-
ferential impedance of 100. Use cables and connec-
tors that have matched differential impedance to
minimize impedance discontinuities.
Avoid the use of unbalanced cables such as coaxial
cable. Balanced cables such as twisted pair offer
superior signal quality and tend to generate less EMI
due to magnetic field canceling effects. Balanced
cables pick up noise as common mode, which is reject-
ed by the LVDS receiver.
MAX9173
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
_______________________________________________________________________________________ 7
Figure 1. Input with Fail-Safe Network
V
CC
IN_-
IN_+
OUT_
45mV
5µA
2.5µA
MAX9173
Termination
The MAX9173 requires an external termination resistor.
The termination resistor should match the differential
impedance of the transmission line. Termination resis-
tance values may range between 90 to 132,
depending on the characteristic impedance of the
transmission medium.
When using the MAX9173, minimize the distance be-
tween the input termination resistors and the MAX9173
receiver inputs. Use 1% surface-mount resistors.
Board Layout
In general, separate the LVDS inputs from single-ended
outputs to reduce crosstalk. Take special care when
routing traces with the QFN package. Ideally, the LVDS
inputs should be separated by 180° from the
LVTTL/LVCMOS outputs to reduce crosstalk.
For LVDS applications, a four-layer PC board that pro-
vides separate layers of power, ground, LVDS inputs, and
output signals is recommended. When using the QFN
package, solder the exposed pad (EP) to the ground
plane using an array of vias for proper heat dissipation.
Chip Information
TRANSISTOR COUNT: 1462
PROCESS: CMOS
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
8 _______________________________________________________________________________________
IN_+
IN_-
OUT_
*50 REQUIRED FOR PULSE GENERATOR.
PULSE
GENERATOR
50*
50*
C
L
Figure 2. Propagation Delay and Transition Time Test Circuit
Figure 3. Propagation Delay and Transition Time Test Waveforms
IN_-
1.3V
1.1V
1.2V (0V DIFFERENTIAL)
IN_+
OUT_
1.5V
V
ID
= 0.2V
V
OL
V
OH
20%
20%
80%
80%
t
PHLD
t
PLHD
t
THL
t
TLH
1.5V
MAX9173
Quad LVDS Line Receiver with Flow-Through
Pinout and “In-Path” Fail-Safe
_______________________________________________________________________________________ 9
Figure 4. High-Impedance Delay Test Circuit
IN_+
EN
EN
IN_-
OUT_
DEVICE
UNDER
TEST
1/4 MAX9173
C
L
INCLUDES LOAD AND TEST JIG CAPACITANCE.
S
1
= V
CC
FOR t
PZL
AND t
PLZ
MEASUREMENTS.
S
1
= GND FOR t
PZH
AND t
PHZ
MEASUREMENTS.
GENERATOR
50
C
L
R
L
S
1
V
CC
1.5V
EN WHEN EN = GND OR OPEN
EN WHEN EN = V
CC
OUTPUT WHEN
V
ID
= -100mV
OUTPUT WHEN
V
ID
= 0
1.5V
1.5V
0.5V
0.5V
t
PLZ
t
PHZ
t
PZL
t
PZH
1.5V
3V
0
3V
V
CC
V
OL
V
OH
GND
0
50%
50%
Figure 5. High-Impedance Delay Waveforms
CHARGE-CURRENT
LIMIT RESISTOR
DISCHARGE
RESISTANCE
STORAGE
CAPACITOR
C
s
100pF
R
C
1M R
D
1500
HIGH-
VOLTAGE
DC
SOURCE
DEVICE
UNDER
TEST
I
P
100%
90%
36.8%
t
RL
TIME
t
DL
CURRENT WAVEFORM
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
I
r
10%
0
0
AMPERES
Figure 6a. Human Body ESD Test Modules Figure 6b. Human Body Current Waveform

MAX9173ESE+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
IC 0/4 RECEIVER LVDS 16SOIC
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet