Powerful Sensing Solutions for a Better Life
Ultra Low Cost ACCELEROMETER
MXC6255XC: Fully Integrated Thermal Acceleromete
MXC6255XC – Ultra Low Cost Accelerometer
© 2010 MEMSIC, Inc.
One Technology Drive, Suite 325 Andover, MA 01810, USA
Tel: +1 978 738 0900 Fax: +1 978 738 0196
www.memsic.com
Information furnished by MEMSIC is believed to be accurate and reliable. However, no responsibility is assumed by MEMSIC for its
use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by
implication or otherwise under any patent or patent rights of MEMSIC. Information presented in this document is the property o
MEMSIC, Inc., is considered proprietary, and is not to be reproduced without the specific written permission of MEMSIC, Inc.
Rev.E(5/26/2014) Formal release date: 5/29/2014
Page 9 of 14
I
2
C Interface
A slave mode I
2
C interface, capable of operating in standard or fast mode, is implemented on the MXC6255XC. The interface uses a serial data line
(SDA) and a serial clock line (SCL) to achieve bi-directional communication between master and slave devices. A master (typically a microprocessor)
initiates all data transfers to and from the device, and generates the SCL clock that synchronizes the data transfer. The SDA pin on the MXC6255XC
operates both as an input and an open drain output. Since the MXC6255XC only operates as a slave device, the SCL pin is always an input. There
are external pull-up resistors on the I
2
C bus lines. Devices that drive the I
2
C bus lines do so through open-drain n-channel driver transistors, creating a
wired NOR type arrangement.
Data on SDA is only allowed to change when SCL is low. A high to low transition on SDA when SCL is high is indicative of a START condition,
whereas a low to high transition on SDA when SCL is high is indicative of a STOP condition. When the interface is not busy, both SCL and SDA are
high. A data transmission is initiated by the master pulling SDA low while SCL is high, generating a START condition. The data transmission occurs
serially in 8 bit bytes, with the MSB transmitted first. During each byte of transmitted data, the master will generate 9 clock pulses. The first 8 clock
pulses are used to clock the data, the 9th clock pulse is for the acknowledge bit. After the 8 bits of data are clocked in, the transmitting device
releases SDA, and the receiving device pulls it down so that it is stable low during the entire 9th clock pulse. By doing this, the receiving device
"acknowledges" that it has received the transmitted byte. If the slave receiver does not generate an acknowledge, then the master device can
generate a STOP condition and abort the transfer. If the master is the receiver in a data transfer, then it must signal the end of data to the slave by not
generating an acknowledge on the last byte that was clocked out of the slave. The slave must release SDA to allow the master to generate a STOP or
repeated START condition.
The master initiates a data transfer by generating a START condition. After a data transmission is complete, the master may terminate the data
transfer by generating a STOP condition. The bus is considered to be free again a certain time after the STOP condition. Alternatively, the master can
keep the bus busy by generating a repeated START condition instead of a STOP condition. This repeated START condition is functionally identical to
a START condition that follows a STOP. Each device that sits on the I
2
C bus has a unique 7 bit address.
The first byte transmitted by the master following a START is used to address the slave device.
The first 7 bits contain the address of the slave device, and the 8th bit is the R/W* bit (read = 1, write = 0; the asterisk indicates active low, and is used
instead of a bar). If the transmitted address matches up to that of the MXC6255XC, then the MXC6255XC will acknowledge receipt of the address,
and prepare to receive or send data.
If the master is writing to the MXC6255XC, then the next byte that the MXC6255XC receives, following the address byte, is loaded into the address
counter internal to the MXC6255XC. The contents of the address counter indicate which register on the MXC6255XC is being accessed. If the master
now wants to write data to the MXC6255XC, it just continues to send 8-bit bytes. Each byte of data is latched into the register on the MXC6255XC that
the address counter points to. The address counter is incremented after the transmission of each byte.
If the master wants to read data from the MXC6255XC, it first needs to write the address of the register it wants to begin reading data from to the
MXC6255XC address counter. It does this by generating a START, followed by the address byte containing the MXC6255XC address, with R/W* = 0.
The next transmitted byte is then loaded into the MXC6255XC address counter. Then, the master repeats the START condition and re-transmits the
MXC6255XC address, but this time with the R/W* bit set to 1. During the next transmission period, a byte of data from the MXC6255XC register that
is addressed by the contents of the address counter will be transmitted from the MXC6255XC to the master. As in the case of the master writing to the
