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LTC3414IFE#PBF

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LTC3414
10
3414fb
Burst Clamp Programming
If the voltage on the SYNC/MODE pin is less than V
IN
by 1V,
Burst Mode operation is enabled. During Burst Mode
Operation, the voltage on the SYNC/MODE pin determines
the burst clamp level, which sets the minimum peak
inductor current, I
BURST
, for each switching cycle accord-
ing to the following equation:
I
A
V
VV
BURST BURST
=
⎛
⎝
⎜
⎞
⎠
⎟
()
69
06
0 383
.
.
–.
V
BURST
is the voltage on the SYNC/MODE pin. I
BURST
can
only be programmed in the range of 0A to 7A. For values
of V
BURST
greater than 1V, I
BURST
is set at 7A. For values
of V
BURST
less than 0.4V, I
BURST
is set at 0A. As the output
load current drops, the peak inductor currents decrease to
keep the output voltage in regulation. When the output
load current demands a peak inductor current that is less
than I
BURST
, the burst clamp will force the peak inductor
current to remain equal to I
BURST
regardless of further
reductions in the load current. Since the average inductor
current is greater than the output load current, the voltage
on the I
TH
pin will decrease. When the I
TH
voltage drops
to 150mV, sleep mode is enabled in which both power
MOSFETs are shut off along with most of the circuitry to
minimize power consumption. All circuitry is turned back
on and the power MOSFETs begin switching again when
the output voltage drops out of regulation. The value for
I
BURST
is determined by the desired amount of output
voltage ripple. As the value of I
BURST
increases, the sleep
period between pulses and the output voltage ripple in-
crease. The burst clamp voltage, V
BURST
, can be set by a
resistor divider from the V
FB
pin to the SGND pin as shown
in Figure 1.
Pulse skipping, which is a compromise between low
output voltage ripple and efficiency, can be implemented
by connecting pin SYNC/MODEto ground. This sets I
BURST
to 0A. In this condition, the peak inductor current is limited
by the minimum on-time of the current comparator. The
lowest output voltage ripple is achieved while still operat-
ing discontinuously. During very light output loads, pulse
skipping allows only a few switching cycles to be skipped
while maintaining the output voltage in regulation.
Frequency Synchronization
The LTC3414’s internal oscillator can be synchronized to
an external clock signal. During synchronization, the top
MOSFET turn-on is locked to the falling edge of the
external frequency source. The synchronization frequency
range is 300kHz to 4MHz. Synchronization only occurs if
the external frequency is greater than the frequency set
by the external resistor. Because slope compensation is
generated by the oscillator’s RC circuit, the external
frequency should be set 25% higher than the frequency
set by the external resistor to ensure that adequate slope
compensation is present.
Soft-Start
The RUN/SS pin provides a means to shut down the
LTC3414 as well as a timer for soft-start. Pulling the
RUN/SS pin below 0.5V places the LTC3414 in a low
quiescent current shutdown state (I
Q
< 1μA).
The LTC3414 contains an internal soft-start clamp that
gradually raises the clamp on I
TH
after the RUN/SS pin is
pulled above 2V. The full current range becomes available
on I
TH
after 1024 switching cycles. If a longer soft-start
period is desired, the clamp on I
TH
can be set externally
with a resistor and capacitor on the RUN/SS pin as shown
in Figure 1. The soft-start duration can be calculated by
using the following formula:
tRC
V
VV
SECONDS
SS SS SS
IN
IN
=
⎛
⎝
⎜
⎞
⎠
⎟
ln
–.
()
18
Efficiency Considerations
The efficiency of a switching regulator is equal to the
output power divided by the input power times 100%. It is
often useful to analyze individual losses to determine what
is limiting the efficiency and which change would produce
the most improvement. Efficiency can be expressed as:
Efficiency = 100% – (L1 + L2 + L3 + ...)
where L1, L2, etc. are the individual losses as a percentage
of input power.
Although all dissipative elements in the circuit produce
losses, two main sources usually account for most of the
losses: V
IN
quiescent current and I
2
R losses.
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LTC3414
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The V
IN
quiescent current loss dominates the efficiency
loss at very low load currents whereas the I
2
R loss
dominates the efficiency loss at medium to high load
currents. In a typical efficiency plot, the efficiency curve at
very low load currents can be misleading since the actual
power lost is of no consequence.
1. The V
IN
quiescent current is due to two components:
the DC bias current as given in the electrical characteristics
and the internal main switch and synchronous switch gate
charge currents. The gate charge current results from
switching the gate capacitance of the internal power
MOSFET switches. Each time the gate is switched from
high to low to high again, a packet of charge dQ moves
from V
IN
to ground. The resulting dQ/dt is the current out
of V
IN
that is typically larger than the DC bias current. In
continuous mode, I
GATECHG
= f(QT + QB) where QT and QB
are the gate charges of the internal top and bottom
switches. Both the DC bias and gate charge losses are
proportional to V
IN
; thus, their effects will be more pro-
nounced at higher supply voltages.
2. I
2
R losses are calculated from the resistances of the
internal switches, R
SW
, and external inductor R
L
. In con-
tinuous mode the average output current flowing through
inductor L is “chopped” between the main switch and the
synchronous switch. Thus, the series resistance looking
into the SW pin is a function of both top and bottom
MOSFET R
DS(ON)
and the duty cycle (DC) as follows:
R
SW
= (R
DS(ON)
TOP)(DC) + (R
DS(ON)
BOT)(1 – DC)
The R
DS(ON)
for both the top and bottom MOSFETs can be
obtained from the Typical Performance Characteristics
curves. To obtain I
2
R losses, simply add R
SW
to R
L
and
multiply the result by the square of the average output
current.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for less
than 2% of the total loss.
Thermal Considerations
In most applications, the LTC3414 does not dissipate
much heat due to its high efficiency.
However, in applications where the LTC3414 is running at
high ambient temperature with low supply voltage and
high duty cycles, such as in dropout, the heat dissipated
may exceed the maximum junction temperature of the
part. If the junction temperature reaches approximately
150°C, both power switches will be turned off and the SW
node will become high impedance.
To avoid the LTC3414 from exceeding the maximum
junction temperature, the user will need to do some
thermal analysis. The goal of the thermal analysis is to
determine whether the power dissipated exceeds the
maximum junction temperature of the part. The tempera-
ture rise is given by:
t
r
= (P
D
)(θ
JA
)
where P
D
is the power dissipated by the regulator and θ
JA
is the thermal resistance from the junction of the die to the
ambient temperature. For the 20-lead exposed TSSOP
package, the θ
JA
is 38°C/W.
The junction temperature, T
J
, is given by:
T
J
= T
A
+ t
r
where T
A
is the ambient temperature.
Note that at higher supply voltages, the junction tempera-
ture is lower due to reduced switch resistance (R
DS(ON)
).
To maximize the thermal performance of the LTC3414, the
exposed pad should be soldered to a ground plane.
Checking Transient Response
The regulator loop response can be checked by looking at
the load transient response. Switching regulators take
several cycles to respond to a step in load current.
When a load step occurs, V
OUT
immediately shifts by an
amount equal to ΔI
LOAD(ESR)
, where ESR is the effective
series resistance of C
OUT
. ΔI
LOAD
also begins to charge or
discharge C
OUT
generating a feedback error signal used by
the regulator to return V
OUT
to its steady-state value.
During this recovery time, V
OUT
can be monitored for
overshoot or ringing that would indicate a stability prob-
lem. The I
TH
pin external components and output capaci-
tor shown in Figure 1 will provide adequate compensation
for most applications.
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Design Example
As a design example, consider using the LTC3414 in an
application with the following specifications:
V
IN
= 2.7V to 4.2V, V
OUT
= 2.5V, I
OUT(MAX)
= 4A,
I
OUT(MIN)
= 100mA, f = 1MHz.
Because efficiency is important at both high and low load
current, Burst Mode operation will be utilized.
First, calculate the timing resistor:
Rkk
OSC
==
308 10
110
10 298
11
6
.•
•
–
Use a standard value of 294k. Next, calculate the inductor
value for about 40% ripple current at maximum V
IN
:
L
V
MHz A
V
V
H=
⎛
⎝
⎜
⎞
⎠
⎟
⎛
⎝
⎜
⎞
⎠
⎟
= μ
25
116
1
25
42
063
.
()(.)
–
.
.
.
Using a 0.47μH inductor results in a maximum ripple
current of:
Δ =
μ
⎛
⎝
⎜
⎞
⎠
⎟
⎛
⎝
⎜
⎞
⎠
⎟
=I
V
MHz H
V
V
A
L
25
1047
1
25
42
215
.
()(. )
–
.
.
.
C
OUT
will be selected based on the ESR that is required to
satisfy the output voltage ripple requirement and the bulk
capacitance needed for loop stability. For this design, a
22μF ceramic capacitor and a 470μF tantalum capacitor
will be used.
C
IN
should be sized for a maximum current rating of:
IA
V
V
V
V
A
RMS RMS
=
⎛
⎝
⎜
⎞
⎠
⎟
=()
.
.
.
.
–.4
25
42
42
25
1196
Decoupling the PV
IN
and SV
IN
pins with two 22μF capaci-
tors and a 330μF tantalum capacitor is adequate for most
applications.
The burst clamp and output voltage can now be pro-
grammed by choosing the values of R1, R2, and R3. The
voltage on pin MODE will be set to 0.49V by the resistor
divider consisting of R2 and R3. A burst clamp voltage of
0.49V will set the minimum inductor current, I
BURST
, as
follows:
IV V
A
V
A
BURST BURST
=
()
⎛
⎝
⎜
⎞
⎠
⎟
=–.
.
.
.0 383
69
06
123
If we set the sum of R2 and R3 to 200k, then the following
equations can be solved:
RR k
R
R
V
V
2 3 200
1
2
3
08
049
+=
+=
.
.
The two equations shown above result in the following
values for R2 and R3: R2 = 78.7k , R3 = 124k. The value
of R1 can now be determined by solving the following
equation.
1
1
202 7
25
08
1 432
+=
=
R
k
V
V
Rk
.
.
.
A value of 432k will be selected for R1. Figure 4 shows the
complete schematic for this design example.
PC Board Layout Checklist
When laying out the printed circuit board, the following
checklist should be used to ensure proper operation of the
LTC3414. Check the following in your layout:
1. A ground plane is recommended. If a ground plane layer
is not used, the signal and power grounds should be
segregated with all small signal components returning to
the SGND pin at one point which is then connected to the
PGND pin close to the LTC3414.
2. Connect the (+) terminal of the input capacitor(s), C
IN
,
as close as possible to the PV
IN
pin. This capacitor
provides the AC current into the internal power MOSFETs.
3. Keep the switching node, SW, away from all sensitive
small signal nodes.
4. Flood all unused areas on all layers with copper.
Flooding with copper will reduce the temperature rise of
power components. You can connect the copper areas to
any DC net (PV
IN
, SV
IN
, V
OUT
, PGND, SGND, or any other
DC rail in your system).
5. Connect the V
FB
pin directly to the feedback resistors.
The resistor divider must be connected between V
OUT
and SGND.
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LTC3414IFE#PBF

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Manufacturer:
Analog Devices / Linear Technology
Description:
Switching Voltage Regulators 4MHz, 4A Synch Step-dwn Regulator I Grade
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