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MMA1631NKWR2

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P44
Sensors
Freescale Semiconductor, Inc. 37
MMA16xxNKW
Table 39. OTP Register Nibble Address Assignments
Bank Address Register Address (Nibble)
Register Description
Bnk[1] Bnk[0] WA[3] WA[2] WA[1] WA[0]
x x0000
UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
x x0001
x x0010
x x0011
x x0100
x x0101
0 00110
0 00111 DEVCFG2[7] Only RD[3] is written to the LOCK_U bit
0 0 1 0 0 0 TYPE[7:6] Only RD[3:2] is written to LPF[1:0]
0 01001
UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
0 01010
0 01011
0 01100
0 01101
0 01110
0 01111
0 10110 DEVCFG1[3:0] Only RD[1:0] is written to AT[1:0]
0 1 0 1 1 1 DEVCFG2[3:0] RD[3:0] is written to ADDR[3:0]
0 1 1 0 0 0 UD01[3:0] RD[3:0] is written to UD01[3:0]
0 1 1 0 0 1 UD02[3:0] RD[3:0] is written to UD02[3:0]
0 1 1 0 1 0 UD03[3:0] RD[3:0] is written to UD03[3:0]
0 1 1 0 1 1 UD04[3:0] RD[3:0] is written to UD04[3:0]
0 1 1 1 0 0 UD05[3:0] RD[3:0] is written to UD05[3:0]
0 1 1 1 0 1 UD06[3:0] RD[3:0] is written to UD06[3:0]
0 1 1 1 1 0 UD07[3:0] RD[3:0] is written to UD07[3:0]
0 11111
UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
1 00110
1 0 0 1 1 1 DEVCFG2[5] Only RD[1] is written to the PCM bit
1 0 1 0 0 0 UD01[7:4] RD[3:0] is written to UD01[7:4]
1 0 1 0 0 1 UD02[7:4] RD[3:0] is written to UD02[7:4]
1 0 1 0 1 0 UD03[7:4] RD[3:0] is written to UD03[7:4]
1 0 1 0 1 1 UD04[7:4] RD[3:0] is written to UD04[7:4]
1 0 1 1 0 0 UD05[7:4] RD[3:0] is written to UD05[7:4]
1 0 1 1 0 1 UD06[7:4] RD[3:0] is written to UD06[7:4]
1 0 1 1 1 0 UD07[7:4] RD[3:0] is written to UD07[7:4]
1 0 1 1 1 1 UD08[7:4] RD[3:0] is written to UD08[7:4]
1 10110
UNUSED No Write to NVM executed, Normal Response: RD[3:0] = Device Address ADDR[3:0]
1 10111
1 11000
1 11001
1 11010
1 11011
1 11100
1 11101
1 11110
1 11111
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38 Freescale Semiconductor, Inc.
MMA16xxNKW
4.2.1.11 Format Control Command
The Format Control command is supported in the following command formats:
• Standard Long Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
The device ignores the Format Control command if the command is in any other format. The device supports the Format Con-
trol command with the DSI Global Address of ‘0000’, but does not provide a response.
The format control registers defined in the DSI Bus Standard V2.5 are shown in Table 44. The reset values assigned to each
register are also indicated.
Table 40. Format Control Command
Data Address Command
CRC
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] C[3] C[2] C[1] C[0]
R/W FA[2] FA[1] FA[0] FD[3] FD[2] FD[1] FD[0] A[3] A[2] A[1] A[0] 1 0 1 0 0 to 8 bits
Table 41. Format Control Command Bit Definitions
Bit Field Definition
C[3:0] Format Control Command = ‘1010’
A[3:0]
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
FD[3:0] Data to be written to the Format Control Register addressed by FA[2:0] if the R/W bit is set to ‘1’.
FA[2:0] The Address of the Format Control Register to read or written.
R/W
Read/Write determines if the register at address FA[2:0] is to be read or written.
1 - Write FD[3:0] to the Format Control Register addressed by FA[2:0]
0 - Read the Format Control Register addressed by FA[2:0]
Table 42. Long Response - Format Control Command
Response
CRC
D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
A[3]A[2]A[1]A[0]0110R/WFA[2]FA[1]FA[0]FD[3]FD[2]FD[1]FD[0]0 to 8 bits
Table 43. Format Control Response Bit Definitions
Bit Field Definition
FD[3:0] The contents of the Format Control Register addressed by FA[2:0].
FA[2:0] The Address of the Format Control Register that was read or written.
R/W
Read/Write indicates if the register at address FA[2:0] was read or written.
1 - FD[3:0] contains the data written to the Format Control Register addressed by FA[2:0]
0 - FD[3:0] contains the contents for the Format Control Register addressed by FA[2:0]
A[3:0] DSI device address. This field contains the device address.
Table 44. Format Control Register Values
Format Control Register
Register Address Reset Values DSI Standard Values
Definition
FA[2] FA[1] FA[0] FD[3] FD[2] FD[1] FD[0] FD[3] FD[2] FD[1] FD[0]
CRC Polynomial - Low Nibble 00000010001
CRC Polynomial = X
4
+ 1
CRC Polynomial - High Nibble 00100010001
Seed - Low Nibble 01010101010
Seed = ‘1010’
Seed - High Nibble 01100000000
CRC Length (0 to 8) 10001000100 CRC Length = 4
Short Word Data Length (8 to 15)10110001000Short Command Length = 8
Reserved 11000000000 N/A
Format Selection 11100000000 N/A
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Freescale Semiconductor, Inc. 39
MMA16xxNKW
The following restrictions apply to format control register operations:
• Writes to the CRC Length Register of values greater than 8 are ignored. The contents of the register are
unchanged.
• Writes to the Short Word Data Length register of values less than 8 are ignored. The contents of the register are
unchanged.
The contents of the Format Selection register determine whether the standard DSI values or the values in the format control
registers are used. If the Format Selection register contains ‘1111’, the Format Control register values are active. Any write to the
Format Control registers will become active upon completion of the write. In this case, the response to a Format Control Com-
mand will maintain the format of the previous command resulting in an invalid response.
A write of ‘0000’ to the Format Selection register activates the standard DSI values.
A write to the Format Selection register of any other value is ignored.
4.2.1.12 Read Register Data Command
The Read Register Data command is supported in the following command formats:
• Standard Long Command
• Enhanced Long Command as configured by the Format Control Command (Reference Section 4.2.1.11)
The device ignores the Register Data command if the command is in any other format, or if the DSI device address is set to
the DSI Global Device Address of ‘0000’.
The read register command uses the byte address definitions shown in Table 2. Readable registers along with their Byte ad-
dresses are shown in Table 2.
Table 45. Read Register Data Command
Data Address Command
CRC
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[3] A[2] A[1] A[0] C[3] C[2] C[1] C[0]
0 0 0 0 RA[3] RA[2] RA[1] RA[0] A[3] A[2] A[1] A[0] 1 0 1 1 0 to 8 bits
Table 46. Read Register Data Command Bit Definitions
Bit Field Definition
C[3:0] Read Register Data Command = ‘1011’
A[3:0]
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
RA[3:0] RA[3:0] contains the byte address of the register to be read.
Table 47. Long Response - Read Register Data Command
Data
CRC
D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
A[3] A[2] A[1] A[0] RA[3] RA[2] RA[1] RA[0] RD[7] RD[6] RD[5] RD[4] RD[3] RD[2] RD[1] RD[0] 0 to 8 bits
Table 48. Read Register Data Response Bit Definitions
Bit Field Definition
RD7:0] RD[7:0] contains the data of the register addressed by RA[3:0].
RA[3:0] RA[3:0] contains the byte address of the register to be read.
A[3:0]
DSI device address. This field contains the device address. This field must match the internal programmed address field. Otherwise, the
command is ignored.
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MMA1631NKWR2

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Accelerometers 312g Z - AXIS
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